def : Pat<(i64 (zext VK1:$src)),
(SUBREG_TO_REG (i64 0),
(KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit)>;
-
+ def : Pat<(i16 (zext VK1:$src)),
+ (EXTRACT_SUBREG
+ (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_16bit)>;
}
// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
let Predicates = [HasAVX512] in {
%mask1 = bitcast <8 x i1> %mask to i8
ret i8 %mask1
}
+
+; CHECK: zext_test1
+; CHECK: kshiftlw
+; CHECK: kshiftrw
+; CHECK: kmovw
+; CHECK:ret
+define i32 @zext_test1(<16 x i32> %a, <16 x i32> %b) {
+ %cmp_res = icmp ugt <16 x i32> %a, %b
+ %cmp_res.i1 = extractelement <16 x i1> %cmp_res, i32 5
+ %res = zext i1 %cmp_res.i1 to i32
+ ret i32 %res
+}
+
+; CHECK: zext_test2
+; CHECK: kshiftlw
+; CHECK: kshiftrw
+; CHECK: kmovw
+; CHECK:ret
+define i16 @zext_test2(<16 x i32> %a, <16 x i32> %b) {
+ %cmp_res = icmp ugt <16 x i32> %a, %b
+ %cmp_res.i1 = extractelement <16 x i1> %cmp_res, i32 5
+ %res = zext i1 %cmp_res.i1 to i16
+ ret i16 %res
+}
+
+; CHECK: zext_test3
+; CHECK: kshiftlw
+; CHECK: kshiftrw
+; CHECK: kmovw
+; CHECK:ret
+define i8 @zext_test3(<16 x i32> %a, <16 x i32> %b) {
+ %cmp_res = icmp ugt <16 x i32> %a, %b
+ %cmp_res.i1 = extractelement <16 x i1> %cmp_res, i32 5
+ %res = zext i1 %cmp_res.i1 to i8
+ ret i8 %res
+}