// TRI doesn't have accurate enough information to model this yet.
if (I.getOperand().getSubReg())
return false;
- // Inline asm instuctions don't remember their constraints.
- if (I->isInlineAsm())
- return false;
const TargetRegisterClass *OpRC =
- TII->getRegClass(I->getDesc(), I.getOperandNo(), TRI);
+ I->getRegClassConstraint(I.getOperandNo(), TII, TRI);
if (OpRC)
NewRC = TRI->getCommonSubClass(NewRC, OpRC);
if (!NewRC || NewRC == OldRC)
"5":
ret void
}
+
+; PR11078
+;
+; A virtual register used by the "foo" inline asm memory operand gets
+; constrained to GR32_ABCD during coalescing. This makes the inline asm
+; impossible to allocate without splitting the live range and reinflating the
+; register class around the inline asm.
+;
+; The constraint originally comes from the TEST8ri optimization of (icmp (and %t0, 1), 0).
+
+@__force_order = external hidden global i32, align 4
+define void @pr11078(i32* %pgd) nounwind {
+entry:
+ %t0 = load i32* %pgd, align 4
+ %and2 = and i32 %t0, 1
+ %tobool = icmp eq i32 %and2, 0
+ br i1 %tobool, label %if.then, label %if.end
+
+if.then:
+ %t1 = tail call i32 asm sideeffect "bar", "=r,=*m,~{dirflag},~{fpsr},~{flags}"(i32* @__force_order) nounwind
+ br label %if.end
+
+if.end:
+ %t6 = inttoptr i32 %t0 to i64*
+ %t11 = tail call i64 asm sideeffect "foo", "=*m,=A,{bx},{cx},1,~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %t6, i32 0, i32 0, i64 0) nounwind
+ ret void
+}