Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83526 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index a7a43d3458e7faa1d1c9481b5a91cdaab144666a..eae2a54fbdb9bb4e7c777e8aa0db5786bcb1458a 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -1681,6 +1681,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
         case MVT::v4i16: Opc = ARM::VST4d16; break;
         case MVT::v2f32:
         case MVT::v2i32: Opc = ARM::VST4d32; break;
+        case MVT::v1i64: Opc = ARM::VST4d64; break;
         }
         SDValue Chain = N->getOperand(0);
         const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,

diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index 40832e52bea814274a95586d467c81b211b1c712..d2231bf160a56de318bfefd3174c6400055f1288 100644 (file)
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -406,6 +406,10 @@ class VST4WB<bits<4> op7_4, string OpcodeStr>
 def  VST4d8   : VST4D<0b0000, "vst4.8">;
 def  VST4d16  : VST4D<0b0100, "vst4.16">;
 def  VST4d32  : VST4D<0b1000, "vst4.32">;
+def  VST4d64  : NLdSt<0,0b00,0b0010,0b1100, (outs),
+                      (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
+                       DPR:$src4), IIC_VST,
+                      "vst1.64\t\\{$src1,$src2,$src3,$src4\\}, $addr", "", []>;
 
 // vst4 to double-spaced even registers.
 def  VST4q8a  : VST4WB<0b0000, "vst4.8">;

diff --git a/lib/Target/ARM/NEONPreAllocPass.cpp b/lib/Target/ARM/NEONPreAllocPass.cpp
index 773ca7e0b19467fadce0966b60dcba76cbca5ad8..19ff0b36711d9459a2cd3ce98190185601939e32 100644 (file)
--- a/lib/Target/ARM/NEONPreAllocPass.cpp
+++ b/lib/Target/ARM/NEONPreAllocPass.cpp
@@ -172,6 +172,7 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
   case ARM::VST4d8:
   case ARM::VST4d16:
   case ARM::VST4d32:
+  case ARM::VST4d64:
   case ARM::VST4LNd8:
   case ARM::VST4LNd16:
   case ARM::VST4LNd32:

diff --git a/test/CodeGen/ARM/vst4.ll b/test/CodeGen/ARM/vst4.ll
index c7d4da0aee8d05b7a904f860bee5f2476723c3ee..d92c017c30b29029556a7bf620738d0e93cadcf8 100644 (file)
--- a/test/CodeGen/ARM/vst4.ll
+++ b/test/CodeGen/ARM/vst4.ll
@@ -32,6 +32,14 @@ define void @vst4f(float* %A, <2 x float>* %B) nounwind {
        ret void
 }
 
+define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind {
+;CHECK: vst4i64:
+;CHECK: vst1.64
+       %tmp1 = load <1 x i64>* %B
+       call void @llvm.arm.neon.vst4.v1i64(i64* %A, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1)
+       ret void
+}
+
 define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind {
 ;CHECK: vst4Qi8:
 ;CHECK: vst4.8
@@ -72,6 +80,7 @@ declare void @llvm.arm.neon.vst4.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8
 declare void @llvm.arm.neon.vst4.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>) nounwind
 declare void @llvm.arm.neon.vst4.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>) nounwind
 declare void @llvm.arm.neon.vst4.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>) nounwind
+declare void @llvm.arm.neon.vst4.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>) nounwind
 
 declare void @llvm.arm.neon.vst4.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>) nounwind
 declare void @llvm.arm.neon.vst4.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>) nounwind