R600/SI: Set bits on SMRD instructions
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 29 Jul 2014 18:51:54 +0000 (18:51 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 29 Jul 2014 18:51:54 +0000 (18:51 +0000)
Set mayStore = 0 and enable named operand table.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214194 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/R600/SIInstrFormats.td

index 00e69ddbeea4b042ac206779268474fb82e8cf76..d7b593d4a60053decb50f3f0c06baffc913c09da 100644 (file)
@@ -185,6 +185,9 @@ class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
 
   let LGKM_CNT = 1;
   let SMRD = 1;
+  let mayStore = 0;
+  let mayLoad = 1;
+  let UseNamedOperandTable = 1;
 }
 
 //===----------------------------------------------------------------------===//