X86: Add a description of the Intel Atom Silvermont CPU.

Currently this is just the atom model with SSE4.2 enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189669 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp
index ad0ac93b6bd3e8f23f8ed44804fba824a691da68..59ca1ba7c9d9996929df6ff7533cda15c81420c8 100644 (file)
--- a/lib/Support/Host.cpp
+++ b/lib/Support/Host.cpp
@@ -265,6 +265,11 @@ std::string sys::getHostCPUName() {
       case 54: // 32 nm Atom Midview
         return "atom";
 
+      case 55: // Intel Atom Silvermont processors
+      case 74:
+      case 77:
+        return "slm";
+
       default: return (Em64T) ? "x86-64" : "i686";
       }
     case 15: {

diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td
index 2c3643dbd2e1d2f029e24566cd333c0274572382..da989ad42d28396dc4a442820531cb8eab0783d9 100644 (file)
--- a/lib/Target/X86/X86.td
+++ b/lib/Target/X86/X86.td
@@ -206,6 +206,15 @@ def : ProcessorModel<"atom", AtomModel,
                       FeatureLEAUsesAG,
                       FeaturePadShortFunctions]>;
 
+// Silvermont.
+def : ProcessorModel<"slm", AtomModel,
+                     [ProcIntelAtom, FeatureSSE42, FeatureCMPXCHG16B,
+                      FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP,
+                      FeatureSlowDivide,
+                      FeatureCallRegIndirect,
+                      FeatureLEAUsesAG,
+                      FeaturePadShortFunctions]>;
+
 // "Arrandale" along with corei3 and corei5
 def : ProcessorModel<"corei7", SandyBridgeModel,
                      [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,