[Thumb2] LDRS?[BH] cannot load to the PC

The Thumb2 LDRS?[BH] instructions are not valid when the destination
register is the PC (these encodings are used for preload hints).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220278 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 7e5c9bcbe7505ed049dbb82dc8af1d56e6563201..807c252486309c9bf0c64477f20f875a18cea656 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -1262,15 +1262,15 @@ defm t2LDR   : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
 
 // Loads with zero extension
 defm t2LDRH  : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
 
 // Loads with zero extension
 defm t2LDRH  : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,

-                      GPR, UnOpFrag<(zextloadi16 node:$Src)>>;
+                      GPRnopc, UnOpFrag<(zextloadi16 node:$Src)>>;

 defm t2LDRB  : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
 defm t2LDRB  : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,

-                      GPR, UnOpFrag<(zextloadi8  node:$Src)>>;
+                      GPRnopc, UnOpFrag<(zextloadi8  node:$Src)>>;

 
 // Loads with sign extension
 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
 
 // Loads with sign extension
 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,

-                      GPR, UnOpFrag<(sextloadi16 node:$Src)>>;
+                      GPRnopc, UnOpFrag<(sextloadi16 node:$Src)>>;

 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,

-                      GPR, UnOpFrag<(sextloadi8  node:$Src)>>;
+                      GPRnopc, UnOpFrag<(sextloadi8  node:$Src)>>;

 
 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
 // Load doubleword
 
 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
 // Load doubleword

diff --git a/test/MC/ARM/thumb2-ldrb-ldrh.s b/test/MC/ARM/thumb2-ldrb-ldrh.s
new file mode 100644 (file)
index 0000000..8c97987
--- /dev/null
+++ b/test/MC/ARM/thumb2-ldrb-ldrh.s
@@ -0,0 +1,51 @@
+@ RUN: not llvm-mc -triple thumbv7a-none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK
+@ RUN: not llvm-mc -triple thumbv7m-none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK
+
+@ Thumb2 LDRS?[BH] are not valid when Rt == PC (these encodings are used for
+@ preload hints).
+@ We don't check the actual error messages here as they are currently not very
+@ helpful, see http://llvm.org/bugs/show_bug.cgi?id=21066.
+
+@ CHECK: error:
+@ CHECK: error:
+@ CHECK: error:
+@ CHECK: error:
+@ CHECK: error:
+  ldrb    pc, [r0, #10]
+  ldrb.w  pc, [r1, #10]
+  ldrb    pc, [r2, #-5]
+  ldrb    pc, [pc, #7]
+  ldrb.w  pc, [pc, #7]
+
+@ CHECK: error:
+@ CHECK: error:
+@ CHECK: error:
+@ CHECK: error:
+@ CHECK: error:
+  ldrsb   pc, [r3, #10]
+  ldrsb.w pc, [r4, #10]
+  ldrsb   pc, [r5, #-5]
+  ldrsb   pc, [pc, #7]
+  ldrsb.w pc, [pc, #7]
+
+@ CHECK: error:
+@ CHECK: error:
+@ CHECK: error:
+@ CHECK: error:
+@ CHECK: error:
+  ldrh    pc, [r6, #10]
+  ldrh.w  pc, [r7, #10]
+  ldrh    pc, [r8, #-5]
+  ldrh    pc, [pc, #7]
+  ldrh.w  pc, [pc, #7]
+
+@ CHECK: error:
+@ CHECK: error:
+@ CHECK: error:
+@ CHECK: error:
+@ CHECK: error:
+  ldrsh   pc, [r9, #10]
+  ldrsh.w pc, [r10, #10]
+  ldrsh   pc, [r11, #-5]
+  ldrsh   pc, [pc, #7]
+  ldrsh.w pc, [pc, #7]