ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108761 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 67ecb722198a6b6ee661a0b15b4cdb94decf1518..926efc4eb7305ce64e40cb400678e41e54a952f1 100644 (file)
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -993,6 +993,11 @@ protected:
     Synthesizable[VT.getSimpleVT().SimpleTy] = isSynthesizable;
   }
 
+  /// findRepresentativeClass - Return the largest legal super-reg register class
+  /// of the specified register class.
+  virtual const TargetRegisterClass *
+  findRepresentativeClass(const TargetRegisterClass *RC) const;
+
   /// computeRegisterProperties - Once all of the register classes are added,
   /// this allows us to compute derived properties we expose.
   void computeRegisterProperties();
@@ -1698,12 +1703,7 @@ private:
 
   /// hasLegalSuperRegRegClasses - Return true if the specified register class
   /// has one or more super-reg register classes that are legal.
-  bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC);
-
-  /// findRepresentativeClass - Return the largest legal super-reg register class
-  /// of the specified register class.
-  const TargetRegisterClass *
-  findRepresentativeClass(const TargetRegisterClass *RC);
+  bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const;
 };
 
 /// GetReturnInfo - Given an LLVM IR type and return type attributes,

diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 5c09db28607341259474715e8833346c735e035d..dafda50a834106d7441b37f527bfc3b0040eab29 100644 (file)
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -664,7 +664,8 @@ bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
 
 /// hasLegalSuperRegRegClasses - Return true if the specified register class
 /// has one or more super-reg register classes that are legal.
-bool TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) {
+bool
+TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{
   if (*RC->superregclasses_begin() == 0)
     return false;
   for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
@@ -679,9 +680,7 @@ bool TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) {
 /// findRepresentativeClass - Return the largest legal super-reg register class
 /// of the specified register class.
 const TargetRegisterClass *
-TargetLowering::findRepresentativeClass(const TargetRegisterClass *RC) {
-  if (!RC) return 0;
-
+TargetLowering::findRepresentativeClass(const TargetRegisterClass *RC) const {
   const TargetRegisterClass *BestRC = RC;
   for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
          E = RC->superregclasses_end(); I != E; ++I) {
@@ -820,8 +819,10 @@ void TargetLowering::computeRegisterProperties() {
   // not a sub-register class / subreg register class) legal register class for
   // a group of value types. For example, on i386, i8, i16, and i32
   // representative would be GR32; while on x86_64 it's GR64.
-  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i)
-    RepRegClassForVT[i] = findRepresentativeClass(RegClassForVT[i]);
+  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
+    const TargetRegisterClass *RC = RegClassForVT[i];
+    RepRegClassForVT[i] = RC ? findRepresentativeClass(RC) : 0;
+  }
 }
 
 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 9b6db1d2336b8f51e85c771ca6688c1e1c109025..9102664c6e9ef82cc9afac9eeab27f63291be32f 100644 (file)
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -550,6 +550,22 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
     benefitFromCodePlacementOpt = true;
 }
 
+const TargetRegisterClass *
+ARMTargetLowering::findRepresentativeClass(const TargetRegisterClass *RC) const{
+  switch (RC->getID()) {
+  default:
+    return RC;
+  case ARM::tGPRRegClassID:
+  case ARM::GPRRegClassID:
+    return ARM::GPRRegisterClass;
+  case ARM::SPRRegClassID:
+  case ARM::DPRRegClassID:
+    return ARM::DPRRegisterClass;
+  case ARM::QPRRegClassID:
+    return ARM::QPRRegisterClass;
+  }
+}
+
 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch (Opcode) {
   default: return 0;

diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h
index 7f37e20724e7117c065e752336574f1e25cf8330..ef47003058c847305498eba20f6a7de4ab860d87 100644 (file)
--- a/lib/Target/ARM/ARMISelLowering.h
+++ b/lib/Target/ARM/ARMISelLowering.h
@@ -271,6 +271,10 @@ namespace llvm {
     /// materialize the FP immediate as a load from a constant pool.
     virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
 
+  protected:
+    const TargetRegisterClass *
+    findRepresentativeClass(const TargetRegisterClass *RC) const;
+
   private:
     /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
     /// make the right decision when generating code for different targets.