Make prolog align stack properly. Make epilog not touch any registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12183 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index 6817b7ec46ead91e7c83768738929fadd754dff0..7acf882db7ca4bd2c9d98080b990160674b6a57e 100644 (file)
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -71,15 +71,15 @@ void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
 
   // Eventually this should emit the correct save instruction based on the
   // number of bytes in the frame.  For now we just hardcode it.
-  BuildMI(MBB, MBB.begin(), V8::SAVEi, 2, V8::SP).addImm(-122).addReg(V8::SP);
+  BuildMI(MBB, MBB.begin(), V8::SAVEri, 2, V8::SP).addImm(-112).addReg(V8::SP);
 }
 
 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
                                        MachineBasicBlock &MBB) const {
   MachineBasicBlock::iterator MBBI = prior(MBB.end());
-  assert(MBBI->getOpcode() == V8::JMPLi &&
-         "Can only put epilog before return instruction!");
-  BuildMI(MBB, MBBI, V8::RESTOREi, 2, V8::O0).addImm(0).addReg(V8::L7);
+  assert(MBBI->getOpcode() == V8::RETL &&
+         "Can only put epilog before 'retl' instruction!");
+  BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
 }
 
 

diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
index 6817b7ec46ead91e7c83768738929fadd754dff0..7acf882db7ca4bd2c9d98080b990160674b6a57e 100644 (file)
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
@@ -71,15 +71,15 @@ void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
 
   // Eventually this should emit the correct save instruction based on the
   // number of bytes in the frame.  For now we just hardcode it.
-  BuildMI(MBB, MBB.begin(), V8::SAVEi, 2, V8::SP).addImm(-122).addReg(V8::SP);
+  BuildMI(MBB, MBB.begin(), V8::SAVEri, 2, V8::SP).addImm(-112).addReg(V8::SP);
 }
 
 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
                                        MachineBasicBlock &MBB) const {
   MachineBasicBlock::iterator MBBI = prior(MBB.end());
-  assert(MBBI->getOpcode() == V8::JMPLi &&
-         "Can only put epilog before return instruction!");
-  BuildMI(MBB, MBBI, V8::RESTOREi, 2, V8::O0).addImm(0).addReg(V8::L7);
+  assert(MBBI->getOpcode() == V8::RETL &&
+         "Can only put epilog before 'retl' instruction!");
+  BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
 }