llvm_report_error already prints "LLVM ERROR:". So stop reporting errors like "LLVM...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77971 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetData.h b/include/llvm/Target/TargetData.h
index c06165c62d0da6070bdabdb381235e59bb63d132..60c2c323d7d06bb906831ff950377dc4b7aedfec 100644 (file)
--- a/include/llvm/Target/TargetData.h
+++ b/include/llvm/Target/TargetData.h
@@ -112,7 +112,7 @@ public:
   /// @note This has to exist, because this is a pass, but it should never be
   /// used.
   TargetData() : ImmutablePass(&ID) {
-    llvm_report_error("ERROR: Bad TargetData ctor used.  "
+    llvm_report_error("Bad TargetData ctor used.  "
                       "Tool did not specify a TargetData to use?");
   }
 

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index b08950d7ec3ac987f203c09b3884a70953c24816..0c410fb75bcbd04d3830ca56430946d1641c1f15 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -5074,7 +5074,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
              Input.ConstraintVT.isInteger()) ||
             (OpInfo.ConstraintVT.getSizeInBits() !=
              Input.ConstraintVT.getSizeInBits())) {
-          llvm_report_error("llvm: error: Unsupported asm: input constraint"
+          llvm_report_error("Unsupported asm: input constraint"
                             " with a matching output constraint of incompatible"
                             " type!");
         }
@@ -5179,7 +5179,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
       // Copy the output from the appropriate register.  Find a register that
       // we can use.
       if (OpInfo.AssignedRegs.Regs.empty()) {
-        llvm_report_error("llvm: error: Couldn't allocate output reg for"
+        llvm_report_error("Couldn't allocate output reg for"
                           " constraint '" + OpInfo.ConstraintCode + "'!");
       }
 
@@ -5233,8 +5233,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
             || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
           // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
           if (OpInfo.isIndirect) {
-            llvm_report_error("llvm: error: "
-                              "Don't know how to handle tied indirect "
+            llvm_report_error("Don't know how to handle tied indirect "
                               "register inputs yet!");
           }
           RegsForValue MatchedRegs;
@@ -5277,7 +5276,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
         TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
                                          hasMemory, Ops, DAG);
         if (Ops.empty()) {
-          llvm_report_error("llvm: error: Invalid operand for inline asm"
+          llvm_report_error("Invalid operand for inline asm"
                             " constraint '" + OpInfo.ConstraintCode + "'!");
         }
 
@@ -5308,7 +5307,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
 
       // Copy the input into the appropriate registers.
       if (OpInfo.AssignedRegs.Regs.empty()) {
-        llvm_report_error("llvm: error: Couldn't allocate input reg for"
+        llvm_report_error("Couldn't allocate input reg for"
                           " constraint '"+ OpInfo.ConstraintCode +"'!");
       }
 

diff --git a/lib/ExecutionEngine/Interpreter/Execution.cpp b/lib/ExecutionEngine/Interpreter/Execution.cpp
index b351ba25c544e838687b28c51f21d13188787228..8d21d1f40b5994175b7f8c1c5422900b6678b986 100644 (file)
--- a/lib/ExecutionEngine/Interpreter/Execution.cpp
+++ b/lib/ExecutionEngine/Interpreter/Execution.cpp
@@ -644,7 +644,7 @@ void Interpreter::visitUnwindInst(UnwindInst &I) {
 }
 
 void Interpreter::visitUnreachableInst(UnreachableInst &I) {
-  llvm_report_error("ERROR: Program executed an 'unreachable' instruction!");
+  llvm_report_error("Program executed an 'unreachable' instruction!");
 }
 
 void Interpreter::visitBranchInst(BranchInst &I) {

diff --git a/lib/ExecutionEngine/JIT/Intercept.cpp b/lib/ExecutionEngine/JIT/Intercept.cpp
index feb13c6ce1555db5b3a6b95b7c47856a14f66ec2..0dde845559e7bdac6f1e8a28ed1b430672c9b30a 100644 (file)
--- a/lib/ExecutionEngine/JIT/Intercept.cpp
+++ b/lib/ExecutionEngine/JIT/Intercept.cpp
@@ -141,7 +141,7 @@ void *JIT::getPointerToNamedFunction(const std::string &Name,
       return RP;
 
   if (AbortOnFailure) {
-    llvm_report_error("ERROR: Program used external function '"+Name+
+    llvm_report_error("Program used external function '"+Name+
                       "' which could not be resolved!");
   }
   return 0;

diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index ef7c95fa927accada08dd15c7e39193032135c8a..7b497a76904f7edd3d4c82510ef0fe9bdbba3482 100644 (file)
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -749,7 +749,7 @@ void Emitter<CodeEmitter>::emitDataProcessingInstruction(
   const TargetInstrDesc &TID = MI.getDesc();
 
   if (TID.Opcode == ARM::BFC) {
-    llvm_report_error("ERROR: ARMv6t2 JIT is not yet supported.");
+    llvm_report_error("ARMv6t2 JIT is not yet supported.");
   }
 
   // Part of binary is determined by TableGn.