let Inst{19-16} = Rn;
let Inst{11-0} = imm;
}
+def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
+ IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
+ [/* For disassembly only; pattern left blank */]> {
+ bits<4> Rd;
+ bits<4> Rn;
+ bits<4> Rm;
+ let Inst{11-4} = 0b00000000;
+ let Inst{25} = 0;
+ let Inst{20} = 1;
+ let Inst{3-0} = Rm;
+ let Inst{15-12} = Rd;
+ let Inst{19-16} = Rn;
+}
def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
[(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {