#include "llvm/Analysis/LoopInfo.h"
#include "llvm/CodeGen/IntrinsicLowering.h"
#include "llvm/Transforms/Scalar.h"
+#include "llvm/Target/TargetMachineRegistry.h"
#include "llvm/Support/CallSite.h"
#include "llvm/Support/CFG.h"
#include "llvm/Support/GetElementPtrTypeIterator.h"
using namespace llvm;
namespace {
+ // Register the target.
+ RegisterTarget<CTargetMachine> X("c", "C backend");
+
/// NameAllUsedStructs - This pass inserts names for any unnamed structure
/// types that are used by the program.
///
// This is the only thing that actually does anything here.
virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
+
+ // This class always works, but shouldn't be the default in most cases.
+ static unsigned getModuleMatchQuality(const Module &M) { return 1; }
};
} // End llvm namespace
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/CodeGen/IntrinsicLowering.h"
#include "llvm/Transforms/Scalar.h"
+#include "llvm/Target/TargetMachineRegistry.h"
#include "llvm/Support/CallSite.h"
#include "llvm/Support/CFG.h"
#include "llvm/Support/GetElementPtrTypeIterator.h"
using namespace llvm;
namespace {
+ // Register the target.
+ RegisterTarget<CTargetMachine> X("c", "C backend");
+
/// NameAllUsedStructs - This pass inserts names for any unnamed structure
/// types that are used by the program.
///
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Target/TargetMachineImpls.h"
+#include "llvm/Target/TargetMachineRegistry.h"
#include "llvm/Transforms/Scalar.h"
+#include <iostream>
using namespace llvm;
+namespace {
+ // Register the target.
+ RegisterTarget<PowerPCTargetMachine> X("powerpc", "PowerPC (experimental)");
+}
+
// allocatePowerPCTargetMachine - Allocate and return a subclass of
// TargetMachine that implements the PowerPC backend.
//
#include "llvm/Module.h"
#include "llvm/PassManager.h"
#include "llvm/Target/TargetMachineImpls.h"
+#include "llvm/Target/TargetMachineRegistry.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/Passes.h"
using namespace llvm;
+namespace {
+ // Register the target.
+ RegisterTarget<PowerPCTargetMachine> X("powerpc", "PowerPC (experimental)");
+}
+
// allocatePowerPCTargetMachine - Allocate and return a subclass of
// TargetMachine that implements the PowerPC backend.
//
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Target/TargetMachineImpls.h"
+#include "llvm/Target/TargetMachineRegistry.h"
#include "llvm/Transforms/Scalar.h"
#include <iostream>
using namespace llvm;
+namespace {
+ // Register the target.
+ RegisterTarget<SparcV8TargetMachine> X("sparcv8", "SPARC V8 (experimental)");
+}
+
// allocateSparcV8TargetMachine - Allocate and return a subclass of
// TargetMachine that implements the SparcV8 backend.
//
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Target/TargetMachineImpls.h"
+#include "llvm/Target/TargetMachineRegistry.h"
#include "llvm/Transforms/Scalar.h"
#include <iostream>
using namespace llvm;
+namespace {
+ // Register the target.
+ RegisterTarget<SparcV8TargetMachine> X("sparcv8", "SPARC V8 (experimental)");
+}
+
// allocateSparcV8TargetMachine - Allocate and return a subclass of
// TargetMachine that implements the SparcV8 backend.
//
#include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Target/TargetMachineImpls.h"
+#include "llvm/Target/TargetMachineRegistry.h"
#include "llvm/Transforms/Scalar.h"
#include "MappingInfo.h"
#include "SparcV9Internals.h"
#include "SparcV9TargetMachine.h"
#include "Support/CommandLine.h"
-
using namespace llvm;
static const unsigned ImplicitRegUseList[] = { 0 }; /* not used yet */
cl::opt<bool> DisableStrip("disable-strip",
cl::desc("Do not strip the LLVM bytecode in executable"));
+
+ // Register the target.
+ RegisterTarget<SparcV9TargetMachine> X("sparcv9", "SPARC V9");
+}
+
+unsigned SparcV9TargetMachine::getJITMatchQuality() {
+#if defined(sparc) || defined(__sparc__) || defined(__sparcv9)
+ return 10;
+#else
+ return 0;
+#endif
+}
+
+unsigned SparcV9TargetMachine::getModuleMatchQuality(const Module &M) {
+ if (M.getEndianness() == Module::BigEndian &&
+ M.getPointerSize() == Module::Pointer64)
+ return 10; // Direct match
+ else if (M.getEndianness() != Module::AnyEndianness ||
+ M.getPointerSize() != Module::AnyPointerSize)
+ return 0; // Match for some other target
+
+ return getJITMatchQuality()/2;
}
//===---------------------------------------------------------------------===//
}
-SparcV9TargetMachine::SparcV9TargetMachine(IntrinsicLowering *il)
+SparcV9TargetMachine::SparcV9TargetMachine(const Module &M,
+ IntrinsicLowering *il)
: TargetMachine("UltraSparcV9-Native", il, false),
schedInfo(*this),
regInfo(*this),
PM.add(createMachineFunctionPrinterPass(&std::cerr, "Final code:\n"));
}
-/// allocateSparcV9TargetMachine - Allocate and return a subclass of TargetMachine
-/// that implements the SparcV9 backend. (the llvm/CodeGen/SparcV9.h interface)
+/// allocateSparcV9TargetMachine - Allocate and return a subclass of
+/// TargetMachine that implements the SparcV9 backend. (the
+/// llvm/CodeGen/SparcV9.h interface)
///
TargetMachine *llvm::allocateSparcV9TargetMachine(const Module &M,
IntrinsicLowering *IL) {
- return new SparcV9TargetMachine(IL);
+ return new SparcV9TargetMachine(M, IL);
}
SparcV9FrameInfo frameInfo;
SparcV9JITInfo jitInfo;
public:
- SparcV9TargetMachine(IntrinsicLowering *IL);
+ SparcV9TargetMachine(const Module &M, IntrinsicLowering *IL);
virtual const TargetInstrInfo *getInstrInfo() const { return &instrInfo; }
virtual const TargetSchedInfo *getSchedInfo() const { return &schedInfo; }
virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
MachineCodeEmitter &MCE);
+
+ static unsigned getModuleMatchQuality(const Module &M);
+ static unsigned getJITMatchQuality();
};
} // End llvm namespace
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Target/TargetMachineImpls.h"
+#include "llvm/Target/TargetMachineRegistry.h"
#include "llvm/Transforms/Scalar.h"
#include "Support/CommandLine.h"
#include "Support/Statistic.h"
"when profiling the code generator."));
cl::opt<bool> NoSimpleISel("disable-simple-isel", cl::init(true),
cl::desc("Use the hand coded 'simple' X86 instruction selector"));
+
+ // Register the target.
+ RegisterTarget<X86TargetMachine> X("x86", "IA-32 (Pentium and above)");
}
// allocateX86TargetMachine - Allocate and return a subclass of TargetMachine
return new X86TargetMachine(M, IL);
}
+unsigned X86TargetMachine::getJITMatchQuality() {
+#if defined(i386) || defined(__i386__) || defined(__x86__)
+ return 10;
+#else
+ return 0;
+#endif
+}
+
+unsigned X86TargetMachine::getModuleMatchQuality(const Module &M) {
+ if (M.getEndianness() == Module::LittleEndian &&
+ M.getPointerSize() == Module::Pointer32)
+ return 10; // Direct match
+ else if (M.getEndianness() != Module::AnyEndianness ||
+ M.getPointerSize() != Module::AnyPointerSize)
+ return 0; // Match for some other target
+
+ return getJITMatchQuality()/2;
+}
/// X86TargetMachine ctor - Create an ILP32 architecture model
///
MachineCodeEmitter &MCE);
virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
+
+ static unsigned getModuleMatchQuality(const Module &M);
+ static unsigned getJITMatchQuality();
};
// this is implemented in X86CodeEmitter.cpp