Add thumb2 sign / zero extend with rotate instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74755 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 85cd2e13ce457b380fdc685ef9d1676696545a8e..9f847bd834fa68d4f85b06f5a40657eb385b3baf 100644 (file)
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -303,7 +303,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,   Expand);
   setOperationAction(ISD::MEMBARRIER,         MVT::Other, Expand);
 
-  if (!Subtarget->hasV6Ops()) {
+  if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
   }

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index fc21982e811701e07d43ed0e7d6808a02ffd6b29..50345a68fdddac65465455766261f144b475e8f2 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -435,6 +435,30 @@ class T2I_picst<string opc, PatFrag opnode> :
           !strconcat("${addr:label}:\n\t", opc), " $src, $addr",
           [(opnode GPR:$src, addrmodepc:$addr)]>;
 
+
+/// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
+/// register and one whose operand is a register rotated by 8/16/24.
+multiclass T2I_unary_rrot<string opc, PatFrag opnode> {
+  def r     : T2I<(outs GPR:$dst), (ins GPR:$Src),
+                  opc, " $dst, $Src",
+                 [(set GPR:$dst, (opnode GPR:$Src))]>;
+  def r_rot : T2I<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
+                  opc, " $dst, $Src, ror $rot",
+                 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>;
+}
+
+/// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
+/// register and one whose operand is a register rotated by 8/16/24.
+multiclass T2I_bin_rrot<string opc, PatFrag opnode> {
+  def rr     : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
+                  opc, " $dst, $LHS, $RHS",
+                  [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>;
+  def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
+                  opc, " $dst, $LHS, $RHS, ror $rot",
+                  [(set GPR:$dst, (opnode GPR:$LHS,
+                                          (rotr GPR:$RHS, rot_imm:$rot)))]>;
+}
+
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
@@ -713,6 +737,40 @@ def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
                      [(set GPR:$dst,
                            (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
 
+//===----------------------------------------------------------------------===//
+//  Extend Instructions.
+//
+
+// Sign extenders
+
+defm t2SXTB  : T2I_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
+defm t2SXTH  : T2I_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
+
+defm t2SXTAB : T2I_bin_rrot<"sxtab",
+                        BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
+defm t2SXTAH : T2I_bin_rrot<"sxtah",
+                        BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
+
+// TODO: SXT(A){B|H}16
+
+// Zero extenders
+
+let AddedComplexity = 16 in {
+defm t2UXTB   : T2I_unary_rrot<"uxtb"  , UnOpFrag<(and node:$Src, 0x000000FF)>>;
+defm t2UXTH   : T2I_unary_rrot<"uxth"  , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
+defm t2UXTB16 : T2I_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
+
+def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
+            (t2UXTB16r_rot GPR:$Src, 24)>;
+def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
+            (t2UXTB16r_rot GPR:$Src, 8)>;
+
+defm t2UXTAB : T2I_bin_rrot<"uxtab",
+                            BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
+defm t2UXTAH : T2I_bin_rrot<"uxtah",
+                            BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
+}
+
 //===----------------------------------------------------------------------===//
 //  Arithmetic Instructions.
 //

diff --git a/test/CodeGen/ARM/sxt_rot.ll b/test/CodeGen/ARM/sxt_rot.ll
index bfecce8bde227fe478f479222ffcb7b8a5ede3ae..e9f302c88d1c06e43168fa39164e9f1d0b9a0a87 100644 (file)
--- a/test/CodeGen/ARM/sxt_rot.ll
+++ b/test/CodeGen/ARM/sxt_rot.ll
@@ -1,8 +1,15 @@
 ; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | \
-; RUN:   grep sxtb | count 1
+; RUN:   grep sxtb | count 2
+; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | \
+; RUN:   grep sxtb | grep ror | count 1
 ; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | \
 ; RUN:   grep sxtab | count 1
 
+define i32 @test0(i8 %A) {
+        %B = sext i8 %A to i32
+       ret i32 %B
+}
+
 define i8 @test1(i32 %A) signext {
        %B = lshr i32 %A, 8
        %C = shl i32 %A, 24

diff --git a/test/CodeGen/Thumb2/thumb2-sxt_rot.ll b/test/CodeGen/Thumb2/thumb2-sxt_rot.ll
new file mode 100644 (file)
index 0000000..4afe354
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-sxt_rot.ll
@@ -0,0 +1,29 @@
+; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN:   grep sxtb | count 2
+; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN:   grep sxtb | grep ror | count 1
+; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN:   grep sxtab | count 1
+
+define i32 @test0(i8 %A) {
+        %B = sext i8 %A to i32
+       ret i32 %B
+}
+
+define i8 @test1(i32 %A) signext {
+       %B = lshr i32 %A, 8
+       %C = shl i32 %A, 24
+       %D = or i32 %B, %C
+       %E = trunc i32 %D to i8
+       ret i8 %E
+}
+
+define i32 @test2(i32 %A, i32 %X) signext {
+       %B = lshr i32 %A, 8
+       %C = shl i32 %A, 24
+       %D = or i32 %B, %C
+       %E = trunc i32 %D to i8
+        %F = sext i8 %E to i32
+        %G = add i32 %F, %X
+       ret i32 %G
+}

diff --git a/test/CodeGen/Thumb2/thumb2-uxt_rot.ll b/test/CodeGen/Thumb2/thumb2-uxt_rot.ll
new file mode 100644 (file)
index 0000000..0d1cc18
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-uxt_rot.ll
@@ -0,0 +1,24 @@
+; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep uxtb | count 1
+; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep uxtab | count 1
+; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | grep uxth | count 1
+
+define i8 @test1(i32 %A.u) zeroext {
+    %B.u = trunc i32 %A.u to i8
+    ret i8 %B.u
+}
+
+define i32 @test2(i32 %A.u, i32 %B.u) zeroext {
+    %C.u = trunc i32 %B.u to i8
+    %D.u = zext i8 %C.u to i32
+    %E.u = add i32 %A.u, %D.u
+    ret i32 %E.u
+}
+
+define i32 @test3(i32 %A.u) zeroext {
+    %B.u = lshr i32 %A.u, 8
+    %C.u = shl i32 %A.u, 24
+    %D.u = or i32 %B.u, %C.u
+    %E.u = trunc i32 %D.u to i16
+    %F.u = zext i16 %E.u to i32
+    ret i32 %F.u
+}

diff --git a/test/CodeGen/Thumb2/thumb2-uxtb.ll b/test/CodeGen/Thumb2/thumb2-uxtb.ll
new file mode 100644 (file)
index 0000000..28a5fe4
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-uxtb.ll
@@ -0,0 +1,74 @@
+; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
+; RUN:   grep uxt | count 10
+
+define i32 @test1(i32 %x) {
+       %tmp1 = and i32 %x, 16711935            ; <i32> [#uses=1]
+       ret i32 %tmp1
+}
+
+define i32 @test2(i32 %x) {
+       %tmp1 = lshr i32 %x, 8          ; <i32> [#uses=1]
+       %tmp2 = and i32 %tmp1, 16711935         ; <i32> [#uses=1]
+       ret i32 %tmp2
+}
+
+define i32 @test3(i32 %x) {
+       %tmp1 = lshr i32 %x, 8          ; <i32> [#uses=1]
+       %tmp2 = and i32 %tmp1, 16711935         ; <i32> [#uses=1]
+       ret i32 %tmp2
+}
+
+define i32 @test4(i32 %x) {
+       %tmp1 = lshr i32 %x, 8          ; <i32> [#uses=1]
+       %tmp6 = and i32 %tmp1, 16711935         ; <i32> [#uses=1]
+       ret i32 %tmp6
+}
+
+define i32 @test5(i32 %x) {
+       %tmp1 = lshr i32 %x, 8          ; <i32> [#uses=1]
+       %tmp2 = and i32 %tmp1, 16711935         ; <i32> [#uses=1]
+       ret i32 %tmp2
+}
+
+define i32 @test6(i32 %x) {
+       %tmp1 = lshr i32 %x, 16         ; <i32> [#uses=1]
+       %tmp2 = and i32 %tmp1, 255              ; <i32> [#uses=1]
+       %tmp4 = shl i32 %x, 16          ; <i32> [#uses=1]
+       %tmp5 = and i32 %tmp4, 16711680         ; <i32> [#uses=1]
+       %tmp6 = or i32 %tmp2, %tmp5             ; <i32> [#uses=1]
+       ret i32 %tmp6
+}
+
+define i32 @test7(i32 %x) {
+       %tmp1 = lshr i32 %x, 16         ; <i32> [#uses=1]
+       %tmp2 = and i32 %tmp1, 255              ; <i32> [#uses=1]
+       %tmp4 = shl i32 %x, 16          ; <i32> [#uses=1]
+       %tmp5 = and i32 %tmp4, 16711680         ; <i32> [#uses=1]
+       %tmp6 = or i32 %tmp2, %tmp5             ; <i32> [#uses=1]
+       ret i32 %tmp6
+}
+
+define i32 @test8(i32 %x) {
+       %tmp1 = shl i32 %x, 8           ; <i32> [#uses=1]
+       %tmp2 = and i32 %tmp1, 16711680         ; <i32> [#uses=1]
+       %tmp5 = lshr i32 %x, 24         ; <i32> [#uses=1]
+       %tmp6 = or i32 %tmp2, %tmp5             ; <i32> [#uses=1]
+       ret i32 %tmp6
+}
+
+define i32 @test9(i32 %x) {
+       %tmp1 = lshr i32 %x, 24         ; <i32> [#uses=1]
+       %tmp4 = shl i32 %x, 8           ; <i32> [#uses=1]
+       %tmp5 = and i32 %tmp4, 16711680         ; <i32> [#uses=1]
+       %tmp6 = or i32 %tmp5, %tmp1             ; <i32> [#uses=1]
+       ret i32 %tmp6
+}
+
+define i32 @test10(i32 %p0) {
+       %tmp1 = lshr i32 %p0, 7         ; <i32> [#uses=1]
+       %tmp2 = and i32 %tmp1, 16253176         ; <i32> [#uses=2]
+       %tmp4 = lshr i32 %tmp2, 5               ; <i32> [#uses=1]
+       %tmp5 = and i32 %tmp4, 458759           ; <i32> [#uses=1]
+       %tmp7 = or i32 %tmp5, %tmp2             ; <i32> [#uses=1]
+       ret i32 %tmp7
+}