let Pattern = pattern;
let isStore = store;
let isLoad = load;
+ let Defs = [R28]; //We may use this for frame index calculations, so reserve it here
bits<5> Ra;
bits<16> disp;
let Inst{20-16} = Rb;
let Inst{15-0} = disp;
}
-class MFormAlt<bits<6> opcode, string asmstr>
- : InstAlphaAlt<opcode, asmstr> {
- bits<5> Ra;
- bits<16> disp;
- bits<5> Rb;
- let Inst{25-21} = Ra;
- let Inst{20-16} = Rb;
- let Inst{15-0} = disp;
-}
class MfcForm<bits<6> opcode, bits<16> fc, string asmstr>
: InstAlpha<opcode, (ops GPRC:$RA), asmstr> {
bits<5> Ra;
}
//3.3.2
-let isBranch = 1, isTerminator = 1 in
-class BForm<bits<6> opcode, string asmstr>
- : InstAlpha<opcode, (ops GPRC:$RA, s21imm:$DISP), asmstr> {
- bits<5> Ra;
- bits<21> disp;
-
- let Inst{25-21} = Ra;
- let Inst{20-0} = disp;
-}
def target : Operand<OtherVT> {}
let isBranch = 1, isTerminator = 1 in
class BFormD<bits<6> opcode, string asmstr, list<dag> pattern>
//load address, rellocated gpdist form
let OperandList = (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in {
-def LDAg : MFormAlt<0x08, "lda $RA,0($RB)\t\t!gpdisp!$NUM">; //Load address
-def LDAHg : MFormAlt<0x09, "ldah $RA,0($RB)\t\t!gpdisp!$NUM">; //Load address
+def LDAg : MForm<0x08, 0, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", []>; //Load address
+def LDAHg : MForm<0x09, 0, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", []>; //Load address
}
//Load quad, rellocated literal form
" for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
if (Offset > IMM_HIGH || Offset < IMM_LOW) {
- std::cerr << "Unconditionally using R28 for evil purposes\n";
+ DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: " << Offset << "\n");
//so in this case, we need to use a temporary register, and move the original
//inst off the SP/FP
//fix up the old: