Trivial typo fixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128996 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html
index 02869f63a45b1bbb550e49c76e74ed39c7d644a5..4a656a243c47fdafe973ad63042074849eb01dd0 100644 (file)
--- a/docs/CodeGenerator.html
+++ b/docs/CodeGenerator.html
@@ -2532,7 +2532,7 @@ OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg,   SignExtImm  PhysReg
 
 <div class="doc_text">
 
-<p>x86 has an feature which provides
+<p>x86 has a feature which provides
    the ability to perform loads and stores to different address spaces
    via the x86 segment registers.  A segment override prefix byte on an
    instruction causes the instruction's memory access to go to the specified

diff --git a/docs/ReleaseNotes.html b/docs/ReleaseNotes.html
index 22f0db34723e633ecd36efe1a7b4f3028e9315c4..f06bc6f8a21e4858e11e4b68259364201ed8ee8d 100644 (file)
--- a/docs/ReleaseNotes.html
+++ b/docs/ReleaseNotes.html
@@ -633,7 +633,7 @@ it run faster:</p>
 </li>
   
 <li>X86 support for FS/GS relative loads and stores using <a 
-    href="CodeGenerator.html#x86_memory">address space 256/257</a> work reliably
+    href="CodeGenerator.html#x86_memory">address space 256/257</a> works reliably
     now.</li>
   
 <li>LLVM 2.9 generates much better code in several cases by using adc/sbb to
@@ -644,7 +644,7 @@ it run faster:</p>
   shorten the height of instruction schedules without inducing register spills.
 </li>
 
-<li>The MC assembler support for 3dNow! and 3DNowA instructions.</li>
+<li>The MC assembler supports 3dNow! and 3DNowA instructions.</li>
   
 <li>Several bugs have been fixed for Windows x64 code generator.</li>
 </ul>