More h-registers tricks: folding zext nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72558 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td
index 77847e474d0e82459cb6741cbc5bebef6eb10601..f58ba8db2b8686eb8076521cb6beea975660f849 100644 (file)
--- a/lib/Target/X86/X86Instr64bit.td
+++ b/lib/Target/X86/X86Instr64bit.td
@@ -1607,6 +1607,13 @@ def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
             (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
                             x86_subreg_8bit_hi))>,
       Requires<[In64BitMode]>;
+def : Pat<(i64 (zext (srl_su GR32:$src, (i8 8)))),
+          (SUBREG_TO_REG
+            (i64 0),
+            (MOVZX32_NOREXrr8
+              (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
+                              x86_subreg_8bit_hi)),
+            x86_subreg_32bit)>;
 def : Pat<(srl_su GR16:$src, (i8 8)),
           (EXTRACT_SUBREG
             (MOVZX32_NOREXrr8
@@ -1614,6 +1621,18 @@ def : Pat<(srl_su GR16:$src, (i8 8)),
                               x86_subreg_8bit_hi)),
             x86_subreg_16bit)>,
       Requires<[In64BitMode]>;
+def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
+          (MOVZX32_NOREXrr8
+            (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
+                            x86_subreg_8bit_hi))>,
+      Requires<[In64BitMode]>;
+def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
+          (SUBREG_TO_REG
+            (i64 0),
+            (MOVZX32_NOREXrr8
+              (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
+                              x86_subreg_8bit_hi)),
+            x86_subreg_32bit)>;
 
 // h-register extract and store.
 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 84c357308a59ebfc92d4e6604be80c6a23fd98cf..50ae41764151bc6136f6fd56a4fa543f81f31967 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -3538,6 +3538,10 @@ def : Pat<(srl_su GR16:$src, (i8 8)),
                               x86_subreg_8bit_hi)),
             x86_subreg_16bit)>,
       Requires<[In32BitMode]>;
+def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
+          (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
+                                      x86_subreg_8bit_hi))>,
+      Requires<[In32BitMode]>;
 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
           (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
                                       x86_subreg_8bit_hi))>,

diff --git a/test/CodeGen/X86/h-registers-3.ll b/test/CodeGen/X86/h-registers-3.ll
new file mode 100644 (file)
index 0000000..d353a22
--- /dev/null
+++ b/test/CodeGen/X86/h-registers-3.ll
@@ -0,0 +1,12 @@
+; RUN: llvm-as < %s | llc -march=x86    | grep mov | count 1
+; RUN: llvm-as < %s | llc -march=x86-64 | grep mov | count 1
+
+define zeroext i8 @foo() nounwind ssp {
+entry:
+  %0 = tail call zeroext i16 (...)* @bar() nounwind
+  %1 = lshr i16 %0, 8
+  %2 = trunc i16 %1 to i8
+  ret i8 %2
+}
+
+declare zeroext i16 @bar(...)

diff --git a/test/CodeGen/X86/remat-mov0.ll b/test/CodeGen/X86/remat-mov0.ll
new file mode 100644 (file)
index 0000000..360628c
--- /dev/null
+++ b/test/CodeGen/X86/remat-mov0.ll
@@ -0,0 +1,40 @@
+; RUN: llvm-as < %s | llc -march=x86 | grep xor | count 2
+
+       %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
+       %struct.ImgT = type { i8, i8*, i8*, %struct.FILE*, i32, i32, i32, i32, i8*, double*, float*, float*, float*, i32*, double, double, i32*, double*, i32*, i32* }
+       %struct._CompT = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, i8, %struct._PixT*, %struct._CompT*, i8, %struct._CompT* }
+       %struct._PixT = type { i32, i32, %struct._PixT* }
+       %struct.__sFILEX = type opaque
+       %struct.__sbuf = type { i8*, i32 }
+
+declare fastcc void @MergeComponents(%struct._CompT*, %struct._CompT*, %struct._CompT*, %struct._CompT**, %struct.ImgT*) nounwind 
+
+define fastcc void @MergeToLeft(%struct._CompT* %comp, %struct._CompT** %head, %struct.ImgT* %img) nounwind  {
+entry:
+       br label %bb208
+
+bb105:         ; preds = %bb200
+       br i1 false, label %bb197, label %bb149
+
+bb149:         ; preds = %bb105
+       %tmp151 = getelementptr %struct._CompT* %comp, i32 0, i32 0             ; <i32*> [#uses=1]
+       br label %bb193
+
+bb193:         ; preds = %bb184, %bb149
+       %tmp196 = load i32* %tmp151, align 4            ; <i32> [#uses=1]
+       br label %bb197
+
+bb197:         ; preds = %bb193, %bb105
+       %last_comp.0 = phi i32 [ %tmp196, %bb193 ], [ 0, %bb105 ]               ; <i32> [#uses=0]
+       %indvar.next = add i32 %indvar, 1               ; <i32> [#uses=1]
+       br label %bb200
+
+bb200:         ; preds = %bb208, %bb197
+       %indvar = phi i32 [ 0, %bb208 ], [ %indvar.next, %bb197 ]               ; <i32> [#uses=2]
+       %xm.0 = sub i32 %indvar, 0              ; <i32> [#uses=1]
+       %tmp202 = icmp slt i32 %xm.0, 1         ; <i1> [#uses=1]
+       br i1 %tmp202, label %bb105, label %bb208
+
+bb208:         ; preds = %bb200, %entry
+       br label %bb200
+}