Move getOpcodeName from the various target InstPrinters into the superclass MCInstPri...
authorBenjamin Kramer <benny.kra@googlemail.com>
Mon, 2 Apr 2012 08:32:38 +0000 (08:32 +0000)
committerBenjamin Kramer <benny.kra@googlemail.com>
Mon, 2 Apr 2012 08:32:38 +0000 (08:32 +0000)
All implementations used the same code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153866 91177308-0d34-0410-b5e6-96231b3b80d8

14 files changed:
include/llvm/MC/MCInstPrinter.h
lib/MC/MCInstPrinter.cpp
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
lib/Target/ARM/InstPrinter/ARMInstPrinter.h
lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
lib/Target/Mips/InstPrinter/MipsInstPrinter.h
lib/Target/PTX/InstPrinter/PTXInstPrinter.cpp
lib/Target/PTX/InstPrinter/PTXInstPrinter.h
lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
lib/Target/X86/InstPrinter/X86ATTInstPrinter.h
lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
lib/Target/X86/InstPrinter/X86IntelInstPrinter.h

index 1823e7b2d343038f4d39bdffd79e60126784c585..3c4f28be7ca6477011bb5732c0aedb7b49431961 100644 (file)
@@ -52,7 +52,7 @@ public:
 
   /// getOpcodeName - Return the name of the specified opcode enum (e.g.
   /// "MOV32ri") or empty if we can't resolve it.
-  virtual StringRef getOpcodeName(unsigned Opcode) const;
+  StringRef getOpcodeName(unsigned Opcode) const;
 
   /// printRegName - Print the assembler register name.
   virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
index 3060ad6003d4176e4e9cb1a8ca19588d11f0e7cb..847bcc0a1604f3cee617a2da5a82f203cc1abcbf 100644 (file)
@@ -8,6 +8,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/MC/MCInstPrinter.h"
+#include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Support/ErrorHandling.h"
@@ -20,7 +21,7 @@ MCInstPrinter::~MCInstPrinter() {
 /// getOpcodeName - Return the name of the specified opcode enum (e.g.
 /// "MOV32ri") or empty if we can't resolve it.
 StringRef MCInstPrinter::getOpcodeName(unsigned Opcode) const {
-  return "";
+  return MII.getName(Opcode);
 }
 
 void MCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
index b654a75a2ebf1f0c8ef53f72f8f1ede8c766190e..b3eeafe083149fd17b350e195a78667b7781e008 100644 (file)
@@ -44,10 +44,6 @@ ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
   setAvailableFeatures(STI.getFeatureBits());
 }
 
-StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
-  return MII.getName(Opcode);
-}
-
 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
   OS << getRegisterName(RegNo);
 }
index d103ca4232c98d6eed50135573f80b6ca181c671..8acb7eef019bb3f23a05ce6e1b6a6a7c4a02c309 100644 (file)
@@ -27,7 +27,6 @@ public:
                  const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
 
   virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
-  virtual StringRef getOpcodeName(unsigned Opcode) const;
   virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
 
   // Autogenerated by tblgen.
index 679082274262635b9503fc22406fa149e09d0128..6886b1745240c888c686b974802c0f44882a1882 100644 (file)
@@ -62,10 +62,6 @@ const char* Mips::MipsFCCToString(Mips::CondCode CC) {
   llvm_unreachable("Impossible condition code!");
 }
 
-StringRef MipsInstPrinter::getOpcodeName(unsigned Opcode) const {
-  return MII.getName(Opcode);
-}
-
 void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
   OS << '$' << StringRef(getRegisterName(RegNo)).lower();
 }
index 8e614740eb358ed96c27ab8f2149225c1b9cfde5..76b839b2127f31b1f892f24772e53fbeec9fe87b 100644 (file)
@@ -85,7 +85,6 @@ public:
   void printInstruction(const MCInst *MI, raw_ostream &O);
   static const char *getRegisterName(unsigned RegNo);
 
-  virtual StringRef getOpcodeName(unsigned Opcode) const;
   virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
   virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
 
index 3aa3b26bf887d63fc472e6a60bffbacf18d8107f..1830213267b847d2a5f80c2cee9c87eee9af01e1 100644 (file)
@@ -36,10 +36,6 @@ PTXInstPrinter::PTXInstPrinter(const MCAsmInfo &MAI,
   setAvailableFeatures(STI.getFeatureBits());
 }
 
-StringRef PTXInstPrinter::getOpcodeName(unsigned Opcode) const {
-  return MII.getName(Opcode);
-}
-
 void PTXInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
   // Decode the register number into type and offset
   unsigned RegSpace  = RegNo & 0x7;
index b01293a99535e00d5967ce9e38fa423599d063be..ea4d50477d708cbf6927ec0f675be2574c15f21a 100644 (file)
@@ -27,7 +27,6 @@ public:
                  const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
 
   virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
-  virtual StringRef getOpcodeName(unsigned Opcode) const;
   virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
 
   // Autogenerated by tblgen.
index 6e85ab926cdb93537d2caa9641775f51c63d9499..61d23ce06aa1ce88d7ab587bd0842e2b10c55b75 100644 (file)
@@ -23,10 +23,6 @@ using namespace llvm;
 
 #include "PPCGenAsmWriter.inc"
 
-StringRef PPCInstPrinter::getOpcodeName(unsigned Opcode) const {
-  return MII.getName(Opcode);
-}
-
 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
   OS << getRegisterName(RegNo);
 }
index d4d3929777b70d6c5a5e645023ee290051c87ee0..73fd5342a1650e8a69f20733b02c8f0d93ec9e09 100644 (file)
@@ -34,7 +34,6 @@ public:
   
   virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
   virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
-  virtual StringRef getOpcodeName(unsigned Opcode) const;
   
   // Autogenerated by tblgen.
   void printInstruction(const MCInst *MI, raw_ostream &O);
index 8bf9058dd5dd2b47acd769fd6bb7d9935abe8b74..5118e4cad4e26db219233b911dde66fce69db95a 100644 (file)
@@ -50,10 +50,6 @@ void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
     EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
 }
 
-StringRef X86ATTInstPrinter::getOpcodeName(unsigned Opcode) const {
-  return MII.getName(Opcode);
-}
-
 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
                                    raw_ostream &O) {
   switch (MI->getOperand(Op).getImm()) {
index 568b7940a767b0f1334c73a8662a8b32ef90cc8b..2e00bff1738e178dbbc882092797badd30b1e5ea 100644 (file)
@@ -28,7 +28,6 @@ public:
 
   virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
   virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
-  virtual StringRef getOpcodeName(unsigned Opcode) const;
 
   // Autogenerated by tblgen, returns true if we successfully printed an
   // alias.
index e37a477b1550e86c80da43efac4a747f45be6a0a..4ea662cbe0c1fdcdda50595fbc2789e7307f5927 100644 (file)
@@ -41,9 +41,6 @@ void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
   if (CommentStream)
     EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
 }
-StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const {
-  return MII.getName(Opcode);
-}
 
 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
                                      raw_ostream &O) {
index c70b141b728d85e6b7f9e127b83d0f400429bbe8..4f5938daf4cdce98a975c10a13a9e44e063576d4 100644 (file)
@@ -29,7 +29,6 @@ public:
 
   virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
   virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
-  virtual StringRef getOpcodeName(unsigned Opcode) const;
   
   // Autogenerated by tblgen.
   void printInstruction(const MCInst *MI, raw_ostream &O);