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correct register class for tADDspi to GPR since the register will always be SP
author
Jim Grosbach
<grosbach@apple.com>
Tue, 12 May 2009 22:30:18 +0000
(22:30 +0000)
committer
Jim Grosbach
<grosbach@apple.com>
Tue, 12 May 2009 22:30:18 +0000
(22:30 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71602
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/ARM/ARMInstrThumb.td
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diff --git
a/lib/Target/ARM/ARMInstrThumb.td
b/lib/Target/ARM/ARMInstrThumb.td
index 914be0390b4b6f3682b6042a01ce5faa8c296ce9..ffb83a8b4d364b583d80eff6b2a7b7b923499254 100644
(file)
--- a/
lib/Target/ARM/ARMInstrThumb.td
+++ b/
lib/Target/ARM/ARMInstrThumb.td
@@
-307,7
+307,7
@@
def tADDrPCi : TI<(outs tGPR:$dst), (ins i32imm:$rhs),
def tADDrSPi : TI<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs),
"add $dst, $sp, $rhs * 4 @ addrspi", []>;
-def tADDspi : TIt<(outs
tGPR:$dst), (ins t
GPR:$lhs, i32imm:$rhs),
+def tADDspi : TIt<(outs
GPR:$dst), (ins
GPR:$lhs, i32imm:$rhs),
"add $dst, $rhs * 4", []>;
def tAND : TIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),