Clean up my own mess.

X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48279 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5a6077a3ca14cc3fd60f6fc805755ed7b0bdba0d..0e719f844e990da7de3304e71af47aac94fe70f6 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1102,14 +1102,8 @@ SDOperand DAGCombiner::visitSUB(SDNode *N) {
   }
   
   // fold (sub x, x) -> 0
-  if (N0 == N1) {
-    if (AfterLegalize && ISD::isBuildVectorAllZeros(N0.Val))
-      // For example, zero vectors might be normalized to a particular vector
-      // type to ensure they are CSE'd. Avoid issuing zero vector nodes of
-      // *unexpected* type after legalization.
-      return N0;
+  if (N0 == N1)
     return DAG.getConstant(0, N->getValueType(0));
-  }
   // fold (sub c1, c2) -> c1-c2
   if (N0C && N1C)
     return DAG.getNode(ISD::SUB, VT, N0, N1);

diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td
index 65013b3914ca71a592fe5c523aa9bc1d6e051171..0a18fa53f1ef34b95d61baedcc991f76c3607159 100644 (file)
--- a/lib/Target/X86/X86InstrMMX.td
+++ b/lib/Target/X86/X86InstrMMX.td
@@ -510,6 +510,12 @@ let isReMaterializable = 1 in {
                               [(set VR64:$dst, (v2i32 immAllOnesV))]>;
 }
 
+let Predicates = [HasMMX] in {
+  def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>;
+  def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>;
+  def : Pat<(v8i8  immAllZerosV), (MMX_V_SET0)>;
+}
+
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
 //===----------------------------------------------------------------------===//

diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 55d92bdfa6a7b159204126927593b678af904aa3..0ca9c69c00399d54bf946fa9a21abc667ad52066 100644 (file)
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -969,6 +969,14 @@ def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
                  "xorps\t$dst, $dst",
                  [(set VR128:$dst, (v4i32 immAllZerosV))]>;
 
+let Predicates = [HasSSE1] in {
+  def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
+  def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
+  def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
+  def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
+  def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
+}
+
 // FR32 to 128-bit vector conversion.
 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
                       "movss\t{$src, $dst|$dst, $src}",