Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with legalizetypes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58714 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 14c4526d1a062eabb0bdd13b26ff1e215b99f356..721213ddc1061fa5556c9a3c0fd541e88bd5843e 100644 (file)
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -214,7 +214,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
 
   if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
-    // Turn f64->i64 into FMRRD iff target supports vfp2.
+    // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
     setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
 
   // We want to custom lower some of our intrinsics.
@@ -1349,13 +1349,19 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
 }
 
 static SDNode *ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
-  // Turn f64->i64 into FMRRD.
-  assert(N->getValueType(0) == MVT::i64 &&
-         N->getOperand(0).getValueType() == MVT::f64);
-  
   SDValue Op = N->getOperand(0);
+  if (N->getValueType(0) == MVT::f64) {
+    // Turn i64->f64 into FMDRR.
+    SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
+                             DAG.getConstant(0, MVT::i32));
+    SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
+                             DAG.getConstant(1, MVT::i32));
+    return DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi).getNode();
+  }
+  
+  // Turn f64->i64 into FMRRD.
   SDValue Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
-                              &Op, 1);
+                            &Op, 1);
   
   // Merge the pieces into a single i64 value.
   return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)).getNode();
@@ -1417,9 +1423,6 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
   case ISD::FRAMEADDR:     break;
   case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
   case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
-      
-      
-  // FIXME: Remove these when LegalizeDAGTypes lands.
   case ISD::BIT_CONVERT:   return SDValue(ExpandBIT_CONVERT(Op.getNode(), DAG), 0);
   case ISD::SRL:
   case ISD::SRA:           return SDValue(ExpandSRx(Op.getNode(), DAG,Subtarget),0);

diff --git a/test/CodeGen/ARM/fixunsdfdi.ll b/test/CodeGen/ARM/fixunsdfdi.ll
new file mode 100644 (file)
index 0000000..d3038b9
--- /dev/null
+++ b/test/CodeGen/ARM/fixunsdfdi.ll
@@ -0,0 +1,29 @@
+; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2
+; RUN: llvm-as < %s | llc -march=arm -mattr=vfp2 | not grep fstd
+
+define hidden i64 @__fixunsdfdi(double %x) nounwind readnone {
+entry:
+       %x14 = bitcast double %x to i64         ; <i64> [#uses=1]
+       br i1 true, label %bb3, label %bb10
+
+bb3:           ; preds = %entry
+       br i1 true, label %bb5, label %bb7
+
+bb5:           ; preds = %bb3
+       %u.in.mask = and i64 %x14, -4294967296          ; <i64> [#uses=1]
+       %.ins = or i64 0, %u.in.mask            ; <i64> [#uses=1]
+       %0 = bitcast i64 %.ins to double                ; <double> [#uses=1]
+       %1 = sub double %x, %0          ; <double> [#uses=1]
+       %2 = fptosi double %1 to i32            ; <i32> [#uses=1]
+       %3 = add i32 %2, 0              ; <i32> [#uses=1]
+       %4 = zext i32 %3 to i64         ; <i64> [#uses=1]
+       %5 = shl i64 %4, 32             ; <i64> [#uses=1]
+       %6 = or i64 %5, 0               ; <i64> [#uses=1]
+       ret i64 %6
+
+bb7:           ; preds = %bb3
+       ret i64 0
+
+bb10:          ; preds = %entry
+       ret i64 0
+}