DAG post-process for Hexagon MI scheduler

This patch introduces a possibility for Hexagon MI scheduler
to perform some target specific post- processing on the scheduling
DAG prior to scheduling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163903 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/lib/Target/Hexagon/HexagonMachineScheduler.cpp
index 3e4b5b6eccd6312797a8e7e5854234b4057b9111..1db6f5ee61db4d78a1a7a48c7c709d56ae0023a1 100644 (file)
--- a/lib/Target/Hexagon/HexagonMachineScheduler.cpp
+++ b/lib/Target/Hexagon/HexagonMachineScheduler.cpp
@@ -20,6 +20,22 @@
 
 using namespace llvm;
 
+/// Platform specific modifications to DAG.
+void VLIWMachineScheduler::postprocessDAG() {
+  SUnit* LastSequentialCall = NULL;
+  // Currently we only catch the situation when compare gets scheduled
+  // before preceding call.
+  for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
+    // Remember the call.
+    if (SUnits[su].getInstr()->isCall())
+      LastSequentialCall = &(SUnits[su]);
+    // Look for a compare that defines a predicate.
+    else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall)
+      SUnits[su].addPred(SDep(LastSequentialCall, SDep::Order, 0, /*Reg=*/0,
+                              false));
+  }
+}
+
 /// Check if scheduling of this SU is possible
 /// in the current packet.
 /// It is _not_ precise (statefull), it is more like
@@ -67,6 +83,13 @@ bool VLIWResourceModel::isResourceAvailable(SUnit *SU) {
 /// Keep track of available resources.
 bool VLIWResourceModel::reserveResources(SUnit *SU) {
   bool startNewCycle = false;
+  // Artificially reset state.
+  if (!SU) {
+    ResourcesModel->clearResources();
+    Packet.clear();
+    TotalPackets++;
+    return false;
+  }
   // If this SU does not fit in the packet
   // start a new one.
   if (!isResourceAvailable(SU)) {
@@ -128,6 +151,9 @@ void VLIWMachineScheduler::schedule() {
 
   buildDAGWithRegPressure();
 
+  // Postprocess the DAG to add platform specific artificial dependencies.
+  postprocessDAG();
+
   // To view Height/Depth correctly, they should be accessed at least once.
   DEBUG(unsigned maxH = 0;
         for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
@@ -354,6 +380,7 @@ SUnit *ConvergingVLIWScheduler::SchedBoundary::pickOnlyChoice() {
   for (unsigned i = 0; Available.empty(); ++i) {
     assert(i <= (HazardRec->getMaxLookAhead() + MaxMinLatency) &&
            "permanent hazard"); (void)i;
+    ResourceModel->reserveResources(0);
     bumpCycle();
     releasePending();
   }

diff --git a/lib/Target/Hexagon/HexagonMachineScheduler.h b/lib/Target/Hexagon/HexagonMachineScheduler.h
index 51829742fff21f03106a34c1cccfd578c23460f6..5b6f226a00e53d121d26483ae9d292e5028f5c8d 100644 (file)
--- a/lib/Target/Hexagon/HexagonMachineScheduler.h
+++ b/lib/Target/Hexagon/HexagonMachineScheduler.h
@@ -114,6 +114,8 @@ public:
   /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
   /// time to do some work.
   virtual void schedule();
+  /// Perform platform specific DAG postprocessing.
+  void postprocessDAG();
 };
 
 /// ConvergingVLIWScheduler shrinks the unscheduled zone using heuristics
@@ -222,6 +224,11 @@ public:
 
   virtual void releaseBottomNode(SUnit *SU);
 
+  unsigned ReportPackets() {
+    return Top.ResourceModel->getTotalPackets() +
+           Bot.ResourceModel->getTotalPackets();
+  }
+
 protected:
   SUnit *pickNodeBidrectional(bool &IsTopNode);