These instructions have access to the complete VSX register file. In addition,
they "swap" the order of the elements so that element 0 (the scalar part) comes
first in memory and element 1 follows at a higher address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204838
91177308-0d34-0410-b5e6-
96231b3b80d8
setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
+ setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
+ setOperationAction(ISD::STORE, MVT::v2f64, Legal);
+
addRegisterClass(MVT::f64, &PPC::VSRCRegClass);
addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
setOperationAction(ISD::ADD, MVT::v2i64, Expand);
setOperationAction(ISD::SUB, MVT::v2i64, Expand);
+ setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
+ AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
+ setOperationAction(ISD::STORE, MVT::v2i64, Promote);
+ AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
+
addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
}
}
def : Pat<(v16i8 (bitconvert v2i64:$A)),
(COPY_TO_REGCLASS $A, VRRC)>;
+def : Pat<(v2f64 (bitconvert v2i64:$A)),
+ (COPY_TO_REGCLASS $A, VRRC)>;
+def : Pat<(v2i64 (bitconvert v2f64:$A)),
+ (COPY_TO_REGCLASS $A, VRRC)>;
+
} // AddedComplexity
} // HasVSX
; CHECK: blr
}
+define <2 x double> @test28(<2 x double>* %a) {
+ %v = load <2 x double>* %a, align 16
+ ret <2 x double> %v
+
+; CHECK-LABEL: @test28
+; CHECK: lxvd2x 34, 0, 3
+; CHECK: blr
+}
+
+define void @test29(<2 x double>* %a, <2 x double> %b) {
+ store <2 x double> %b, <2 x double>* %a, align 16
+ ret void
+
+; CHECK-LABEL: @test29
+; CHECK: stxvd2x 34, 0, 3
+; CHECK: blr
+}
+
+define <2 x i64> @test30(<2 x i64>* %a) {
+ %v = load <2 x i64>* %a, align 16
+ ret <2 x i64> %v
+
+; CHECK-LABEL: @test30
+; CHECK: lxvd2x 34, 0, 3
+; CHECK: blr
+}
+
+define void @test31(<2 x i64>* %a, <2 x i64> %b) {
+ store <2 x i64> %b, <2 x i64>* %a, align 16
+ ret void
+
+; CHECK-LABEL: @test31
+; CHECK: stxvd2x 34, 0, 3
+; CHECK: blr
+}
+