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5a4bf22)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222791
91177308-0d34-0410-b5e6-
96231b3b80d8
s10ExtPred:$src2))]>, ImmRegRel;
// Nop.
s10ExtPred:$src2))]>, ImmRegRel;
// Nop.
-let neverHasSideEffects = 1, isCodeGenOnly = 0 in
-def NOP : ALU32_rr<(outs), (ins),
- "nop",
- []>;
+let hasSideEffects = 0 in
+def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
+ let IClass = 0b0111;
+ let Inst{27-24} = 0b1111;
+}
// Rd32=sub(#s10,Rs32)
let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
// Rd32=sub(#s10,Rs32)
let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 10,
HexagonMCInst Nop;
StringRef NoAnnot;
HexagonMCInst Nop;
StringRef NoAnnot;
- Nop.setOpcode (Hexagon::NOP);
+ Nop.setOpcode (Hexagon::A2_nop);
Nop.setPacketStart (MI->isPacketStart());
printInst (&Nop, O, NoAnnot);
}
Nop.setPacketStart (MI->isPacketStart());
printInst (&Nop, O, NoAnnot);
}