All addressing modes are now exposed. The only remaining relocated forms

are for function prologue.

TODO: move external symbols over to using RelLit.
    : have a pattern that matches constpool|globaladdr
    : have a pattern that matches (add x imm) -> x, imm or (...) -> ..., 0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25003 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 838841d1f80884e807323931930ee66697b89afe..5eddf5dde9fd674a56e931172283513e17e558da 100644 (file)
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -212,12 +212,6 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
     Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg());
     return CurDAG->SelectNodeTo(N, Alpha::LDAr, MVT::i64, CPI, Tmp);
   }
-  case ISD::TargetGlobalAddress: {
-    GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
-    SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
-    return CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64, GA, 
-                                getGlobalBaseReg());
-  }
   case ISD::ExternalSymbol:
     return CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64, 
                                 CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(), MVT::i64),

diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 8d2ffa7177e92dda7edaadff2dc624d7b98e8865..472265939c2178346adba13cc9dfe7dc02c2c6bd 100644 (file)
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -459,7 +459,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
       SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
       return Lo;
     } else
-      return GA;
+      return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
   }
 
   }

diff --git a/lib/Target/Alpha/AlphaISelLowering.h b/lib/Target/Alpha/AlphaISelLowering.h
index 16ff79d5ca3e33a7aa2bfce803f4bcd0cbf419c8..038184d745a8ea30b8fd47cf905ddd2e0000548c 100644 (file)
--- a/lib/Target/Alpha/AlphaISelLowering.h
+++ b/lib/Target/Alpha/AlphaISelLowering.h
@@ -29,12 +29,11 @@ namespace llvm {
       ITOFT_, FTOIT_, CVTQT_, CVTQS_, CVTTQ_,
 
       /// GPRelHi/GPRelLo - These represent the high and low 16-bit
-      /// parts of a global address respectively.  These nodes have
-      /// two operands, the first of which must be a
-      /// TargetGlobalAddress, and the second of which must be a
-      /// Constant.  Selected naively, these turn into 'ldah R(G)' and
-      /// 'lda R(C)', though these are usually folded into other nodes.
-      GPRelHi, GPRelLo,
+      /// parts of a global address respectively.
+      GPRelHi, GPRelLo, 
+
+      /// RetLit - Literal Relocation of a Global
+      RelLit,
 
       /// GlobalBaseReg, used to restore the GOT ptr
       GlobalBaseReg,

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 80e18e7325ba889518a2575719d623a61672a9da..e6a06645975bc0238987a3952eaa75966dc035d6 100644 (file)
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -744,20 +744,13 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
     else assert(0 && "unknown Lo part");
     return Result;
 
-  case ISD::GlobalAddress:
-    AlphaLowering.restoreGP(BB);
-    has_sym = true;
-
-    Reg = Result = MakeReg(MVT::i64);
-
-    if (EnableAlphaLSMark)
-      BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
-        .addImm(getUID());
-
+  case AlphaISD::RelLit: {
+    GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N.getOperand(0));
     BuildMI(BB, Alpha::LDQl, 2, Result)
-      .addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal())
-      .addReg(Alpha::R29);
+      .addGlobalAddress(GASD->getGlobal())
+      .addReg(SelectExpr(N.getOperand(1)));
     return Result;
+  }
 
   case ISD::ExternalSymbol:
     AlphaLowering.restoreGP(BB);

diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td
index fd6bab9d8a1f485b83dc1cdfa5bfee28d092523d..31321843e3372680a10c58c9c9ad4a83c4a69a09 100644 (file)
--- a/lib/Target/Alpha/AlphaInstrInfo.td
+++ b/lib/Target/Alpha/AlphaInstrInfo.td
@@ -27,6 +27,7 @@ def Alpha_cvtqs : SDNode<"AlphaISD::CVTQS_", SDTFPUnaryOpUnC, []>;
 def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_", SDTFPUnaryOp, []>;
 def Alpha_gprello : SDNode<"AlphaISD::GPRelLo", SDTIntBinOp, []>;
 def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi", SDTIntBinOp, []>;
+def Alpha_rellit : SDNode<"AlphaISD::RelLit", SDTIntBinOp, []>;
 
 // These are target-independent nodes, but have target-specific formats.
 def SDT_AlphaCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i64> ]>;
@@ -505,6 +506,26 @@ def LDTr : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)\t\t!gprellow",
                [(set F8RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))]>;
 }
 
+
+//constpool rels
+def : Pat<(i64 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
+          (LDQr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(i64 (sextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i32)),
+          (LDLr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(i64 (zextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i8)),
+          (LDBUr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(i64 (zextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i16)),
+          (LDWUr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(i64 (Alpha_gprello tconstpool:$DISP, GPRC:$RB)),
+          (LDAr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(i64 (Alpha_gprelhi tconstpool:$DISP, GPRC:$RB)),
+          (LDAHr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(f32 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
+          (LDSr tconstpool:$DISP, GPRC:$RB)>;
+def : Pat<(f64 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
+          (LDTr tconstpool:$DISP, GPRC:$RB)>;
+
+
 //misc ext patterns
 def : Pat<(i64 (extload (add GPRC:$RB, immSExt16:$DISP), i8)),
           (LDBU   immSExt16:$DISP, GPRC:$RB)>;
@@ -533,6 +554,19 @@ def : Pat<(i64 (extload GPRC:$addr, i16)),
 def : Pat<(i64 (extload GPRC:$addr, i32)),
           (LDL  0, GPRC:$addr)>;
 
+def : Pat<(store GPRC:$DATA, GPRC:$addr),
+          (STQ  GPRC:$DATA, 0, GPRC:$addr)>;
+def : Pat<(store F8RC:$DATA, GPRC:$addr),
+          (STT  F8RC:$DATA, 0, GPRC:$addr)>;
+def : Pat<(store F4RC:$DATA, GPRC:$addr),
+          (STS  F4RC:$DATA, 0, GPRC:$addr)>;
+def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i32),
+          (STL  GPRC:$DATA, 0, GPRC:$addr)>;
+def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i16),
+          (STW GPRC:$DATA, 0, GPRC:$addr)>;
+def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i8),
+          (STB GPRC:$DATA, 0, GPRC:$addr)>;
+
 
 //load address, rellocated gpdist form
 let OperandList = (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in {
@@ -541,8 +575,9 @@ def LDAHg : MFormAlt<0x09, "ldah $RA,0($RB)\t\t!gpdisp!$NUM">;  //Load address
 }
 
 //Load quad, rellocated literal form
-let isLoad = 1, OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in
-def LDQl : MFormAlt<0x29, "ldq $RA,$DISP($RB)\t\t!literal">; //Load quadword
+let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in
+def LDQl : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!literal",
+                 [(set GPRC:$RA, (Alpha_rellit tglobaladdr:$DISP, GPRC:$RB))]>;
 
 //Branches, int
 def BEQ : BForm<0x39,  "beq $RA,$DISP">; //Branch if = zero