revert r98270.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98281 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 88e2fa15ee74d30a918cf4c21b34a8ddc3a03c6e..9b7f6fc6aeee5178826b43e7b0f3677748817d08 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -2091,7 +2091,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
     // tailcall must happen after callee-saved registers are poped.
     // FIXME: Give it a special register class that contains caller-saved
     // register instead?
-    unsigned TCReg = Is64Bit ? X86::R11 : X86::ECX;
+    unsigned TCReg = Is64Bit ? X86::R11 : X86::EAX;
     Chain = DAG.getCopyToReg(Chain,  dl,
                              DAG.getRegister(TCReg, getPointerTy()),
                              Callee,InFlag);
@@ -2145,7 +2145,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
     }
 
     assert(((Callee.getOpcode() == ISD::Register &&
-               (cast<RegisterSDNode>(Callee)->getReg() == X86::ECX ||
+               (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX ||
                 cast<RegisterSDNode>(Callee)->getReg() == X86::R11)) ||
               Callee.getOpcode() == ISD::TargetExternalSymbol ||
               Callee.getOpcode() == ISD::TargetGlobalAddress) &&

diff --git a/test/CodeGen/X86/tailcallfp2.ll b/test/CodeGen/X86/tailcallfp2.ll
index 8bfae1bb8de5695a25928ca3ff7b2aaffa6a1ff2..3841f518976b7bf21f1f900612e0bb7a3905b04d 100644 (file)
--- a/test/CodeGen/X86/tailcallfp2.ll
+++ b/test/CodeGen/X86/tailcallfp2.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -tailcallopt | grep {jmp} | grep {\\*%ecx}
+; RUN: llc < %s -march=x86 -tailcallopt | grep {jmp} | grep {\\*%eax}
 
 declare i32 @putchar(i32)