#ifndef LLVM_CODEGEN_MACHINEBASICBLOCK_H
#define LLVM_CODEGEN_MACHINEBASICBLOCK_H
-#include <vector>
+#include "llvm/CodeGen/MachineInstr.h"
+#include "Support/ilist"
namespace llvm {
class BasicBlock;
-class MachineInstr;
-template <typename T> struct ilist_traits;
class MachineBasicBlock {
- std::vector<MachineInstr*> Insts;
+public:
+ typedef ilist<MachineInstr> Instructions;
+ Instructions Insts;
MachineBasicBlock *Prev, *Next;
const BasicBlock *BB;
public:
///
const BasicBlock *getBasicBlock() const { return BB; }
- typedef std::vector<MachineInstr*>::iterator iterator;
- typedef std::vector<MachineInstr*>::const_iterator const_iterator;
+ typedef ilist<MachineInstr>::iterator iterator;
+ typedef ilist<MachineInstr>::const_iterator const_iterator;
typedef std::reverse_iterator<const_iterator> const_reverse_iterator;
typedef std::reverse_iterator<iterator> reverse_iterator;
unsigned size() const { return Insts.size(); }
bool empty() const { return Insts.empty(); }
- MachineInstr * operator[](unsigned i) const { return Insts[i]; }
- MachineInstr *&operator[](unsigned i) { return Insts[i]; }
+ const MachineInstr& operator[](unsigned i) const {
+ const_iterator it = Insts.begin();
+ std::advance(it, i);
+ return *it;
+ }
+ MachineInstr& operator[](unsigned i) {
+ iterator it = Insts.begin();
+ std::advance(it, i);
+ return *it;
+ }
- MachineInstr *front() const { return Insts.front(); }
- MachineInstr *back() const { return Insts.back(); }
+ MachineInstr& front() { return Insts.front(); }
+ MachineInstr& back() { return Insts.back(); }
iterator begin() { return Insts.begin(); }
const_iterator begin() const { return Insts.begin(); }
iterator insert(iterator I, MachineInstr *M) { return Insts.insert(I, M); }
// erase - Remove the specified element or range from the instruction list.
- // These functions do not delete any instructions removed.
+ // These functions delete any instructions removed.
//
iterator erase(iterator I) { return Insts.erase(I); }
iterator erase(iterator I, iterator E) { return Insts.erase(I, E); }
-
- MachineInstr *pop_back() {
- MachineInstr *R = back();
- Insts.pop_back();
- return R;
- }
+ MachineInstr* remove(iterator &I) { return Insts.remove(I); }
private: // Methods used to maintain doubly linked list of blocks...
friend class ilist_traits<MachineBasicBlock>;
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "Support/Annotation.h"
-#include "Support/ilist"
namespace llvm {
class TargetMachine;
class GlobalValue;
+template <typename T> class ilist_traits;
+
typedef int MachineOpCode;
//===----------------------------------------------------------------------===//
unsigned opCodeFlags; // flags modifying instrn behavior
std::vector<MachineOperand> operands; // the operands
unsigned numImplicitRefs; // number of implicit operands
-
+ MachineInstr* prev, *next; // links for our intrusive list
// OperandComplete - Return true if it's illegal to add a new operand
bool OperandsComplete() const;
MachineInstr(const MachineInstr &); // DO NOT IMPLEMENT
void operator=(const MachineInstr&); // DO NOT IMPLEMENT
+
+private:
+ // Intrusive list support
+ //
+ friend class ilist_traits<MachineInstr>;
+ MachineInstr() { /* this is for ilist use only to create the sentinel */ }
+ MachineInstr* getPrev() const { return prev; }
+ MachineInstr* getNext() const { return next; }
+
+ void setPrev(MachineInstr* mi) { prev = mi; }
+ void setNext(MachineInstr* mi) { next = mi; }
+
public:
MachineInstr(int Opcode, unsigned numOperands);
#ifndef LLVM_TARGET_MREGISTERINFO_H
#define LLVM_TARGET_MREGISTERINFO_H
-#include "llvm/CodeGen/MachineBasicBlock.h"
#include <cassert>
namespace llvm {
class Type;
+class MachineBasicBlock;
class MachineFunction;
+class MachineInstr;
/// MRegisterDesc - This record contains all of the information known about a
/// particular register. The AliasSet field (if not null) contains a pointer to
//
virtual int storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
+ MachineInstr* MI,
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const = 0;
virtual int loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
+ MachineInstr* MI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const = 0;
virtual int copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
+ MachineInstr* MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const = 0;
/// instructions added to (negative if removed from) the basic block.
///
virtual int eliminateCallFramePseudoInstr(MachineFunction &MF,
- MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &I) const {
+ MachineBasicBlock &MBB,
+ MachineInstr* MI) const {
assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
"eliminateCallFramePseudoInstr must be implemented if using"
" call frame setup/destroy pseudo instructions!");
/// added to (negative if removed from) the basic block.
///
virtual int eliminateFrameIndex(MachineFunction &MF,
- MachineBasicBlock::iterator &II) const = 0;
+ MachineInstr* MI) const = 0;
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function. The return value is the number of instructions
// some NOPs from delay slots. Also, PHIs are not included in the schedule.
unsigned numInstr = 0;
for (MachineBasicBlock::iterator I=MBB.begin(); I != MBB.end(); ++I)
- if (! mii.isNop((*I)->getOpcode()) &&
- ! mii.isDummyPhiInstr((*I)->getOpcode()))
+ if (! mii.isNop(I->getOpcode()) &&
+ ! mii.isDummyPhiInstr(I->getOpcode()))
++numInstr;
assert(S.isched.getNumInstructions() >= numInstr &&
"Lost some non-NOP instructions during scheduling!");
// First find the dummy instructions at the start of the basic block
MachineBasicBlock::iterator I = MBB.begin();
for ( ; I != MBB.end(); ++I)
- if (! mii.isDummyPhiInstr((*I)->getOpcode()))
+ if (! mii.isDummyPhiInstr(I->getOpcode()))
break;
- // Erase all except the dummy PHI instructions from MBB, and
+ // Remove all except the dummy PHI instructions from MBB, and
// pre-allocate create space for the ones we will put back in.
- MBB.erase(I, MBB.end());
+ while (I != MBB.end()) MBB.remove(I);
InstrSchedule::const_iterator NIend = S.isched.end();
for (InstrSchedule::const_iterator NI = S.isched.begin(); NI != NIend; ++NI)
//
unsigned int firstDelaySlotIdx = node->getOrigIndexInBB() + 1;
MachineBasicBlock& MBB = node->getMachineBasicBlock();
- assert(MBB[firstDelaySlotIdx - 1] == brInstr &&
+ assert(&MBB[firstDelaySlotIdx - 1] == brInstr &&
"Incorrect instr. index in basic block for brInstr");
// First find all useful instructions already in the delay slots
// and USE THEM. We'll throw away the unused alternatives below
//
for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx + ndelays; ++i)
- if (! mii.isNop(MBB[i]->getOpcode()))
+ if (! mii.isNop(MBB[i].getOpcode()))
sdelayNodeVec.insert(sdelayNodeVec.begin(),
- graph->getGraphNodeForInstr(MBB[i]));
+ graph->getGraphNodeForInstr(&MBB[i]));
// Then find the NOPs and keep only as many as are needed.
// Put the rest in nopNodeVec to be deleted.
for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx + ndelays; ++i)
- if (mii.isNop(MBB[i]->getOpcode()))
+ if (mii.isNop(MBB[i].getOpcode()))
if (sdelayNodeVec.size() < ndelays)
- sdelayNodeVec.push_back(graph->getGraphNodeForInstr(MBB[i]));
+ sdelayNodeVec.push_back(graph->getGraphNodeForInstr(&MBB[i]));
else {
- nopNodeVec.push_back(graph->getGraphNodeForInstr(MBB[i]));
+ nopNodeVec.push_back(graph->getGraphNodeForInstr(&MBB[i]));
//remove the MI from the Machine Code For Instruction
const TerminatorInst *TI = MBB.getBasicBlock()->getTerminator();
for(MachineCodeForInstruction::iterator mciI=llvmMvec.begin(),
mciE=llvmMvec.end(); mciI!=mciE; ++mciI){
- if (*mciI==MBB[i])
+ if (*mciI == &MBB[i])
llvmMvec.erase(mciI);
}
}
//
delayNodeVec.clear();
for (unsigned i=0; i < MBB.size(); ++i)
- if (MBB[i] != brInstr &&
- mii.getNumDelaySlots(MBB[i]->getOpcode()) > 0)
+ if (&MBB[i] != brInstr &&
+ mii.getNumDelaySlots(MBB[i].getOpcode()) > 0)
{
- SchedGraphNode* node = graph->getGraphNodeForInstr(MBB[i]);
+ SchedGraphNode* node = graph->getGraphNodeForInstr(&MBB[i]);
ReplaceNopsWithUsefulInstr(S, node, delayNodeVec, graph);
}
}
SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
int indexInBB, const TargetMachine& Target)
- : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(mbb ? (*mbb)[indexInBB] : 0) {
+ : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb),
+ MI(mbb ? &(*mbb)[indexInBB] : (MachineInstr*)0) {
if (MI) {
MachineOpCode mopCode = MI->getOpcode();
latency = Target.getInstrInfo().hasResultInterlock(mopCode)
// all preceding instructions in the basic block. Use 0 latency again.
//
for (unsigned i=0, N=MBB.size(); i < N; i++) {
- if (MBB[i] == termMvec[first]) // reached the first branch
+ if (&MBB[i] == termMvec[first]) // reached the first branch
break;
- SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
+ SchedGraphNode* fromNode = this->getGraphNodeForInstr(&MBB[i]);
if (fromNode == NULL)
continue; // dummy instruction, e.g., PHI
// the terminator) that also have delay slots, add an outgoing edge
// from the instruction to the instructions in the delay slots.
//
- unsigned d = mii.getNumDelaySlots(MBB[i]->getOpcode());
+ unsigned d = mii.getNumDelaySlots(MBB[i].getOpcode());
assert(i+d < N && "Insufficient delay slots for instruction?");
for (unsigned j=1; j <= d; j++) {
- SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
+ SchedGraphNode* toNode = this->getGraphNodeForInstr(&MBB[i+j]);
assert(toNode && "No node for machine instr in delay slot?");
(void) new SchedGraphEdge(fromNode, toNode,
SchedGraphEdge::CtrlDep,
// Build graph nodes for each VM instruction and gather def/use info.
// Do both those together in a single pass over all machine instructions.
for (unsigned i=0; i < MBB.size(); i++)
- if (!mii.isDummyPhiInstr(MBB[i]->getOpcode())) {
+ if (!mii.isDummyPhiInstr(MBB[i].getOpcode())) {
SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
- noteGraphNodeForInstr(MBB[i], node);
+ noteGraphNodeForInstr(&MBB[i], node);
// Remember all register references and value defs
findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec,
// Then add incoming def-use (SSA) edges for each machine instruction.
for (unsigned i=0, N=MBB.size(); i < N; i++)
- addEdgesForInstruction(*MBB[i], valueToDefVecMap, target);
+ addEdgesForInstruction(MBB[i], valueToDefVecMap, target);
// Then add edges for dependences on machine registers
this->addMachineRegEdges(regToRefVecMap, target);
for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
mi != miEnd; ++mi) {
- inserted = mi2iMap_.insert(std::make_pair(*mi, miIndex)).second;
+ inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second;
assert(inserted && "multiple MachineInstr -> index mappings");
miIndex += 2;
}
const MachineBasicBlock* mbb = mbbi;
unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
- for (MachineBasicBlock::const_iterator mii = mbb->begin(),
- mie = mbb->end(); mii != mie; ++mii) {
- MachineInstr* mi = *mii;
-
+ for (MachineBasicBlock::const_iterator mi = mbb->begin(),
+ mie = mbb->end(); mi != mie; ++mi) {
for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
- MachineOperand& mop = mi->getOperand(i);
+ const MachineOperand& mop = mi->getOperand(i);
if (mop.isRegister() &&
MRegisterInfo::isVirtualRegister(mop.getReg())) {
unsigned reg = mop.getAllocatedRegNum();
if (vi.AliveBlocks[i]) {
MachineBasicBlock* mbb = lv_->getIndexMachineBasicBlock(i);
if (!mbb->empty()) {
- interval->addRange(getInstructionIndex(mbb->front()),
- getInstructionIndex(mbb->back()) + 1);
+ interval->addRange(getInstructionIndex(&mbb->front()),
+ getInstructionIndex(&mbb->back()) + 1);
}
}
}
// we consider defs to happen at the second time slot of the
// instruction
- unsigned instrIndex = getInstructionIndex(*mi) + 1;
+ unsigned instrIndex = getInstructionIndex(mi) + 1;
bool killedInDefiningBasicBlock = false;
for (int i = 0, e = vi.Kills.size(); i != e; ++i) {
MachineInstr* killerInstr = vi.Kills[i].second;
unsigned start = (mbb == killerBlock ?
instrIndex :
- getInstructionIndex(killerBlock->front()));
- unsigned end = (killerInstr == *mi ?
+ getInstructionIndex(&killerBlock->front()));
+ unsigned end = (killerInstr == mi ?
instrIndex + 1 : // dead
getInstructionIndex(killerInstr) + 1); // killed
// we do not want to add invalid ranges. these can happen when
}
if (!killedInDefiningBasicBlock) {
- unsigned end = getInstructionIndex(mbb->back()) + 1;
+ unsigned end = getInstructionIndex(&mbb->back()) + 1;
interval->addRange(instrIndex, end);
}
}
// we consider defs to happen at the second time slot of the
// instruction
unsigned start, end;
- start = end = getInstructionIndex(*mi) + 1;
+ start = end = getInstructionIndex(mi) + 1;
// a variable can be dead by the instruction defining it
- for (KillIter ki = lv_->dead_begin(*mi), ke = lv_->dead_end(*mi);
+ for (KillIter ki = lv_->dead_begin(mi), ke = lv_->dead_end(mi);
ki != ke; ++ki) {
if (reg == ki->second) {
DEBUG(std::cerr << " dead\n");
do {
++mi;
end += 2;
- for (KillIter ki = lv_->killed_begin(*mi), ke = lv_->killed_end(*mi);
+ for (KillIter ki = lv_->killed_begin(mi), ke = lv_->killed_end(mi);
ki != ke; ++ki) {
if (reg == ki->second) {
DEBUG(std::cerr << " killed\n");
for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
mi != miEnd; ++mi) {
- MachineInstr* instr = *mi;
const TargetInstrDescriptor& tid =
- tm_->getInstrInfo().get(instr->getOpcode());
- DEBUG(std::cerr << "\t[" << getInstructionIndex(instr) << "] ";
- instr->print(std::cerr, *tm_););
+ tm_->getInstrInfo().get(mi->getOpcode());
+ DEBUG(std::cerr << "\t[" << getInstructionIndex(mi) << "] ";
+ mi->print(std::cerr, *tm_););
// handle implicit defs
for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
handleRegisterDef(mbb, mi, *id);
// handle explicit defs
- for (int i = instr->getNumOperands() - 1; i >= 0; --i) {
- MachineOperand& mop = instr->getOperand(i);
+ for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
+ MachineOperand& mop = mi->getOperand(i);
// handle register defs - build intervals
if (mop.isRegister() && mop.isDef())
handleRegisterDef(mbb, mi, mop.getAllocatedRegNum());
const TargetInstrInfo& tii = tm_->getInstrInfo();
- for (MachineFunction::const_iterator mbbi = mf_->begin(),
- mbbe = mf_->end(); mbbi != mbbe; ++mbbi) {
- const MachineBasicBlock* mbb = mbbi;
+ for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
+ mbbi != mbbe; ++mbbi) {
+ MachineBasicBlock* mbb = mbbi;
DEBUG(std::cerr << "machine basic block: "
<< mbb->getBasicBlock()->getName() << "\n");
- for (MachineBasicBlock::const_iterator mii = mbb->begin(),
- mie = mbb->end(); mii != mie; ++mii) {
- MachineInstr* mi = *mii;
+ for (MachineBasicBlock::iterator mi = mbb->begin(), mie = mbb->end();
+ mi != mie; ++mi) {
const TargetInstrDescriptor& tid =
tm_->getInstrInfo().get(mi->getOpcode());
DEBUG(std::cerr << "\t\tinstruction["
// Loop over all of the instructions, processing them.
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
I != E; ++I) {
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
const TargetInstrDescriptor &MID = TII.get(MI->getOpcode());
// Process all of the operands of the instruction...
MachineBasicBlock *Succ = BBMap.find(*SI)->second.first;
// PHI nodes are guaranteed to be at the top of the block...
- for (MachineBasicBlock::iterator I = Succ->begin(), E = Succ->end();
- I != E && (*I)->getOpcode() == TargetInstrInfo::PHI; ++I) {
- MachineInstr *MI = *I;
+ for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end();
+ MI != ME && MI->getOpcode() == TargetInstrInfo::PHI; ++MI) {
for (unsigned i = 1; ; i += 2)
if (MI->getOperand(i+1).getMachineBasicBlock() == MBB) {
MachineOperand &MO = MI->getOperand(i);
for (unsigned i=0, N=tempVec.size(); i < N; i++)
delete tempVec[i];
- // Free the MachineInstr objects allocated, if any.
- for (unsigned i=0, N = size(); i < N; i++)
- delete (*this)[i];
+ // do not free the MachineInstr objects allocated. they are managed
+ // by the ilist in MachineBasicBlock
// Free the CallArgsDescriptor if it exists.
delete callArgsDesc;
return new Printer(OS, Banner);
}
-namespace {
- struct Deleter : public MachineFunctionPass {
- const char *getPassName() const { return "Machine Code Deleter"; }
-
- bool runOnMachineFunction(MachineFunction &MF) {
- // Delete all of the MachineInstrs out of the function. When the sparc
- // backend gets fixed, this can be dramatically simpler, but actually
- // putting this stuff into the MachineBasicBlock destructor!
- for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E;
- ++BB)
- while (!BB->empty())
- delete BB->pop_back();
-
- // Delete the annotation from the function now.
- MachineFunction::destruct(MF.getFunction());
- return true;
- }
- };
-}
-
-/// MachineCodeDeletion Pass - This pass deletes all of the machine code for
-/// the current function, which should happen after the function has been
-/// emitted to a .s file or to memory.
-FunctionPass *llvm::createMachineCodeDeleter() {
- return new Deleter();
-}
-
-
//===---------------------------------------------------------------------===//
// MachineFunction implementation
//===---------------------------------------------------------------------===//
OS << "\n" << LBB->getName() << " (" << (const void*)LBB << "):\n";
for (MachineBasicBlock::const_iterator I = BB->begin(); I != BB->end();++I){
OS << "\t";
- (*I)->print(OS, Target);
+ I->print(OS, Target);
}
}
OS << "\nEnd function \"" << Fn->getName() << "\"\n\n";
/// predecessor basic blocks.
///
bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
- if (MBB.empty() || MBB.front()->getOpcode() != TargetInstrInfo::PHI)
+ if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI)
return false; // Quick exit for normal case...
LiveVariables *LV = getAnalysisToUpdate<LiveVariables>();
const TargetInstrInfo &MII = MF.getTarget().getInstrInfo();
const MRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
- while (MBB.front()->getOpcode() == TargetInstrInfo::PHI) {
- MachineInstr *MI = MBB.front();
+ while (MBB.front().getOpcode() == TargetInstrInfo::PHI) {
// Unlink the PHI node from the basic block... but don't delete the PHI yet
- MBB.erase(MBB.begin());
-
+ MachineBasicBlock::iterator begin = MBB.begin();
+ MachineInstr *MI = MBB.remove(begin);
+
assert(MRegisterInfo::isVirtualRegister(MI->getOperand(0).getReg()) &&
"PHI node doesn't write virt reg?");
//
MachineBasicBlock::iterator AfterPHIsIt = MBB.begin();
while (AfterPHIsIt != MBB.end() &&
- (*AfterPHIsIt)->getOpcode() == TargetInstrInfo::PHI)
+ AfterPHIsIt->getOpcode() == TargetInstrInfo::PHI)
++AfterPHIsIt; // Skip over all of the PHI nodes...
RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC);
// Update live variable information if there is any...
if (LV) {
- MachineInstr *PHICopy = *(AfterPHIsIt-1);
+ MachineInstr *PHICopy = --AfterPHIsIt;
// Add information to LiveVariables to know that the incoming value is
// killed. Note that because the value is defined in several places (once
if (I != opBlock.begin()) { // Handle empty blocks
--I;
// must backtrack over ALL the branches in the previous block
- while (MII.isTerminatorInstr((*I)->getOpcode()) &&
+ while (MII.isTerminatorInstr(I->getOpcode()) &&
I != opBlock.begin())
--I;
// move back to the first branch instruction so new instructions
// are inserted right in front of it and not in front of a non-branch
- if (!MII.isTerminatorInstr((*I)->getOpcode()))
+ if (!MII.isTerminatorInstr(I->getOpcode()))
++I;
}
bool HaveNotEmitted = true;
if (I != opBlock.begin()) {
- MachineInstr *PrevInst = *(I-1);
+ MachineBasicBlock::iterator PrevInst = I;
+ --PrevInst;
for (unsigned i = 0, e = PrevInst->getNumOperands(); i != e; ++i) {
MachineOperand &MO = PrevInst->getOperand(i);
if (MO.isRegister() && MO.getReg() == IncomingReg)
// Loop over all of the PHIs in this successor, checking to see if
// the register is being used...
for (MachineBasicBlock::iterator BBI = MBB->begin(), E=MBB->end();
- BBI != E && (*BBI)->getOpcode() == TargetInstrInfo::PHI;
+ BBI != E && BBI->getOpcode() == TargetInstrInfo::PHI;
++BBI)
- for (unsigned i = 1, e = (*BBI)->getNumOperands(); i < e; i += 2)
- if ((*BBI)->getOperand(i).getReg() == SrcReg) {
+ for (unsigned i = 1, e = BBI->getNumOperands(); i < e; i += 2)
+ if (BBI->getOperand(i).getReg() == SrcReg) {
ValueIsLive = true;
break;
}
// we can add a kill marker to the copy we inserted saying that it
// kills the incoming value!
//
- if (!ValueIsLive)
- LV->addVirtualRegisterKilled(SrcReg, &opBlock, *(I-1));
+ if (!ValueIsLive) {
+ MachineBasicBlock::iterator Prev = I;
+ --Prev;
+ LV->addVirtualRegisterKilled(SrcReg, &opBlock, Prev);
+ }
}
}
}
// really delete the PHI instruction now!
delete MI;
}
-
return true;
}
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB)
for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); )
- if ((*I)->getOpcode() == FrameSetupOpcode ||
- (*I)->getOpcode() == FrameDestroyOpcode) {
- assert((*I)->getNumOperands() == 1 && "Call Frame Setup/Destroy Pseudo"
+ if (I->getOpcode() == FrameSetupOpcode ||
+ I->getOpcode() == FrameDestroyOpcode) {
+ assert(I->getNumOperands() == 1 && "Call Frame Setup/Destroy Pseudo"
" instructions should have a single immediate argument!");
- unsigned Size = (*I)->getOperand(0).getImmedValue();
+ unsigned Size = I->getOperand(0).getImmedValue();
if (Size > MaxCallFrameSize) MaxCallFrameSize = Size;
HasCalls = true;
- RegInfo->eliminateCallFramePseudoInstr(Fn, *BB, I);
+ RegInfo->eliminateCallFramePseudoInstr(Fn, *BB, I++);
} else {
- for (unsigned i = 0, e = (*I)->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = (*I)->getOperand(i);
+ for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = I->getOperand(i);
if (MO.isRegister() && MO.isDef()) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Register allocation must be performed!");
const TargetInstrInfo &TII = Fn.getTarget().getInstrInfo();
for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI) {
// If last instruction is a return instruction, add an epilogue
- if (!FI->empty() && TII.isReturn(FI->back()->getOpcode())) {
- MBB = FI; I = MBB->end()-1;
+ if (!FI->empty() && TII.isReturn(FI->back().getOpcode())) {
+ MBB = FI;
+ I = MBB->end(); --I;
for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
const TargetRegisterClass *RC = RegInfo->getRegClass(RegsToSave[i]);
const TargetInstrInfo &TII = Fn.getTarget().getInstrInfo();
for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
// If last instruction is a return instruction, add an epilogue
- if (!I->empty() && TII.isReturn(I->back()->getOpcode()))
+ if (!I->empty() && TII.isReturn(I->back().getOpcode()))
Fn.getTarget().getRegisterInfo()->emitEpilogue(Fn, *I);
}
}
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB)
for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ++I)
- for (unsigned i = 0, e = (*I)->getNumOperands(); i != e; ++i)
- if ((*I)->getOperand(i).isFrameIndex()) {
+ for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
+ if (I->getOperand(i).isFrameIndex()) {
// If this instruction has a FrameIndex operand, we need to use that
// target machine register info object to eliminate it.
MRI.eliminateFrameIndex(Fn, I);
for (currentInstr_ = currentMbb_->begin();
currentInstr_ != currentMbb_->end(); ) {
DEBUG(std::cerr << "\tinstruction: ";
- (*currentInstr_)->print(std::cerr, *tm_););
+ currentInstr_->print(std::cerr, *tm_););
// use our current mapping and actually replace and
// virtual register with its allocated physical registers
DEBUG(std::cerr << "\t\treplacing virtual registers with mapped "
"physical registers:\n");
- for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
+ for (unsigned i = 0, e = currentInstr_->getNumOperands();
i != e; ++i) {
- MachineOperand& op = (*currentInstr_)->getOperand(i);
+ MachineOperand& op = currentInstr_->getOperand(i);
if (op.isRegister() &&
MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtReg = op.getReg();
if (it != v2pMap_.end()) {
DEBUG(std::cerr << "\t\t\t%reg" << it->first
<< " -> " << mri_->getName(it->second) << '\n');
- (*currentInstr_)->SetMachineOperandReg(i, it->second);
+ currentInstr_->SetMachineOperandReg(i, it->second);
}
}
}
unsigned srcReg, dstReg;
- if (tii.isMoveInstr(**currentInstr_, srcReg, dstReg) &&
+ if (tii.isMoveInstr(*currentInstr_, srcReg, dstReg) &&
((MRegisterInfo::isPhysicalRegister(srcReg) &&
MRegisterInfo::isPhysicalRegister(dstReg) &&
srcReg == dstReg) ||
(MRegisterInfo::isVirtualRegister(srcReg) &&
MRegisterInfo::isVirtualRegister(dstReg) &&
v2ssMap_[srcReg] == v2ssMap_[dstReg]))) {
- delete *currentInstr_;
currentInstr_ = currentMbb_->erase(currentInstr_);
++numPeep;
DEBUG(std::cerr << "\t\tdeleting instruction\n");
Regs toClear;
Regs toSpill;
- const unsigned numOperands = (*currentInstr_)->getNumOperands();
+ const unsigned numOperands = currentInstr_->getNumOperands();
DEBUG(std::cerr << "\t\tloading temporarily used operands to "
"registers:\n");
for (unsigned i = 0; i != numOperands; ++i) {
- MachineOperand& op = (*currentInstr_)->getOperand(i);
+ MachineOperand& op = currentInstr_->getOperand(i);
if (op.isRegister() && op.isUse() &&
MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtReg = op.getAllocatedRegNum();
else
toClear.push_back(it);
}
- (*currentInstr_)->SetMachineOperandReg(i, physReg);
+ currentInstr_->SetMachineOperandReg(i, physReg);
}
}
DEBUG(std::cerr << "\t\tassigning temporarily defined operands to "
"registers:\n");
for (unsigned i = 0; i != numOperands; ++i) {
- MachineOperand& op = (*currentInstr_)->getOperand(i);
+ MachineOperand& op = currentInstr_->getOperand(i);
if (op.isRegister() &&
MRegisterInfo::isVirtualRegister(op.getReg())) {
assert(!op.isUse() && "we should not have uses here!");
// this instruction
toSpill.push_back(it);
}
- (*currentInstr_)->SetMachineOperandReg(i, physReg);
+ currentInstr_->SetMachineOperandReg(i, physReg);
}
}
++currentInstr_; // spills will go after this instruction
void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
// loop over each instruction
- MachineBasicBlock::iterator I = MBB.begin();
- for (; I != MBB.end(); ++I) {
- MachineInstr *MI = *I;
+ MachineBasicBlock::iterator MI = MBB.begin();
+ for (; MI != MBB.end(); ++MI) {
const TargetInstrDescriptor &TID = TM->getInstrInfo().get(MI->getOpcode());
DEBUG(std::cerr << "\nStarting RegAlloc of: " << *MI;
std::cerr << " Regs have values: ";
!MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) {
unsigned VirtSrcReg = MI->getOperand(i).getAllocatedRegNum();
- unsigned PhysSrcReg = reloadVirtReg(MBB, I, VirtSrcReg);
+ unsigned PhysSrcReg = reloadVirtReg(MBB, MI, VirtSrcReg);
MI->SetMachineOperandReg(i, PhysSrcReg); // Assign the input register
}
if (MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
MRegisterInfo::isPhysicalRegister(MI->getOperand(i).getReg())) {
unsigned Reg = MI->getOperand(i).getAllocatedRegNum();
- spillPhysReg(MBB, I, Reg, true); // Spill any existing value in the reg
+ spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in the reg
PhysRegsUsed[Reg] = 0; // It is free and reserved now
PhysRegsUseOrder.push_back(Reg);
for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
*ImplicitDefs; ++ImplicitDefs) {
unsigned Reg = *ImplicitDefs;
- spillPhysReg(MBB, I, Reg);
+ spillPhysReg(MBB, MI, Reg);
PhysRegsUseOrder.push_back(Reg);
PhysRegsUsed[Reg] = 0; // It is free and reserved now
for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
// If DestVirtReg already has a value, use it.
if (!(DestPhysReg = getOrInsertVirt2PhysRegMapSlot(DestVirtReg)))
- DestPhysReg = getReg(MBB, I, DestVirtReg);
+ DestPhysReg = getReg(MBB, MI, DestVirtReg);
markVirtRegModified(DestVirtReg);
MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register
}
// Rewind the iterator to point to the first flow control instruction...
const TargetInstrInfo &TII = TM->getInstrInfo();
- I = MBB.end();
- while (I != MBB.begin() && TII.isTerminatorInstr((*(I-1))->getOpcode()))
- --I;
+ MI = MBB.end();
+ while (MI != MBB.begin() && TII.isTerminatorInstr((--MI)->getOpcode()));
+ ++MI;
// Spill all physical registers holding virtual registers now.
for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
if (PhysRegsUsed[i] != -1)
if (unsigned VirtReg = PhysRegsUsed[i])
- spillVirtReg(MBB, I, VirtReg, i);
+ spillVirtReg(MBB, MI, VirtReg, i);
else
removePhysReg(i);
void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// loop over each instruction
- for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
+ for (MachineBasicBlock::iterator MI = MBB.begin(); MI != MBB.end(); ++MI) {
// Made to combat the incorrect allocation of r2 = add r1, r1
std::map<unsigned, unsigned> Virt2PhysRegMap;
- MachineInstr *MI = *I;
-
RegsUsed.resize(MRegisterInfo::FirstVirtualRegister);
// a preliminary pass that will invalidate any registers that
} else {
physReg = getFreeReg(virtualReg);
}
- ++I;
- spillVirtReg(MBB, I, virtualReg, physReg);
- --I;
+ ++MI;
+ spillVirtReg(MBB, MI, virtualReg, physReg);
+ --MI;
} else {
- physReg = reloadVirtReg(MBB, I, virtualReg);
+ physReg = reloadVirtReg(MBB, MI, virtualReg);
Virt2PhysRegMap[virtualReg] = physReg;
}
}
for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
mbbi != mbbe; ++mbbi) {
- for (MachineBasicBlock::iterator mii = mbbi->begin();
- mii != mbbi->end(); ++mii) {
- MachineInstr* mi = *mii;
+ for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
+ mi != me; ++mi) {
unsigned opcode = mi->getOpcode();
// ignore if it is not a two-address instruction
const TargetRegisterClass* rc =
MF.getSSARegMap()->getRegClass(regA);
- unsigned Added = MRI.copyRegToReg(*mbbi, mii, regA, regB, rc);
+ unsigned Added = MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
numInstrsAdded += Added;
- MachineInstr* prevMi = *(mii - 1);
+ MachineBasicBlock::iterator prevMi = mi;
+ --prevMi;
DEBUG(std::cerr << "\t\tadded instruction: ";
prevMi->print(std::cerr, TM));
PM.add(createRegisterAllocator());
PM.add(createPrologEpilogCodeInserter());
// <insert assembly code output passes here>
- PM.add(createMachineCodeDeleter());
return true; // change to `return false' when this actually works.
}
// some NOPs from delay slots. Also, PHIs are not included in the schedule.
unsigned numInstr = 0;
for (MachineBasicBlock::iterator I=MBB.begin(); I != MBB.end(); ++I)
- if (! mii.isNop((*I)->getOpcode()) &&
- ! mii.isDummyPhiInstr((*I)->getOpcode()))
+ if (! mii.isNop(I->getOpcode()) &&
+ ! mii.isDummyPhiInstr(I->getOpcode()))
++numInstr;
assert(S.isched.getNumInstructions() >= numInstr &&
"Lost some non-NOP instructions during scheduling!");
// First find the dummy instructions at the start of the basic block
MachineBasicBlock::iterator I = MBB.begin();
for ( ; I != MBB.end(); ++I)
- if (! mii.isDummyPhiInstr((*I)->getOpcode()))
+ if (! mii.isDummyPhiInstr(I->getOpcode()))
break;
- // Erase all except the dummy PHI instructions from MBB, and
+ // Remove all except the dummy PHI instructions from MBB, and
// pre-allocate create space for the ones we will put back in.
- MBB.erase(I, MBB.end());
+ while (I != MBB.end()) MBB.remove(I);
InstrSchedule::const_iterator NIend = S.isched.end();
for (InstrSchedule::const_iterator NI = S.isched.begin(); NI != NIend; ++NI)
//
unsigned int firstDelaySlotIdx = node->getOrigIndexInBB() + 1;
MachineBasicBlock& MBB = node->getMachineBasicBlock();
- assert(MBB[firstDelaySlotIdx - 1] == brInstr &&
+ assert(&MBB[firstDelaySlotIdx - 1] == brInstr &&
"Incorrect instr. index in basic block for brInstr");
// First find all useful instructions already in the delay slots
// and USE THEM. We'll throw away the unused alternatives below
//
for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx + ndelays; ++i)
- if (! mii.isNop(MBB[i]->getOpcode()))
+ if (! mii.isNop(MBB[i].getOpcode()))
sdelayNodeVec.insert(sdelayNodeVec.begin(),
- graph->getGraphNodeForInstr(MBB[i]));
+ graph->getGraphNodeForInstr(&MBB[i]));
// Then find the NOPs and keep only as many as are needed.
// Put the rest in nopNodeVec to be deleted.
for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx + ndelays; ++i)
- if (mii.isNop(MBB[i]->getOpcode()))
+ if (mii.isNop(MBB[i].getOpcode()))
if (sdelayNodeVec.size() < ndelays)
- sdelayNodeVec.push_back(graph->getGraphNodeForInstr(MBB[i]));
+ sdelayNodeVec.push_back(graph->getGraphNodeForInstr(&MBB[i]));
else {
- nopNodeVec.push_back(graph->getGraphNodeForInstr(MBB[i]));
+ nopNodeVec.push_back(graph->getGraphNodeForInstr(&MBB[i]));
//remove the MI from the Machine Code For Instruction
const TerminatorInst *TI = MBB.getBasicBlock()->getTerminator();
for(MachineCodeForInstruction::iterator mciI=llvmMvec.begin(),
mciE=llvmMvec.end(); mciI!=mciE; ++mciI){
- if (*mciI==MBB[i])
+ if (*mciI == &MBB[i])
llvmMvec.erase(mciI);
}
}
//
delayNodeVec.clear();
for (unsigned i=0; i < MBB.size(); ++i)
- if (MBB[i] != brInstr &&
- mii.getNumDelaySlots(MBB[i]->getOpcode()) > 0)
+ if (&MBB[i] != brInstr &&
+ mii.getNumDelaySlots(MBB[i].getOpcode()) > 0)
{
- SchedGraphNode* node = graph->getGraphNodeForInstr(MBB[i]);
+ SchedGraphNode* node = graph->getGraphNodeForInstr(&MBB[i]);
ReplaceNopsWithUsefulInstr(S, node, delayNodeVec, graph);
}
}
SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
int indexInBB, const TargetMachine& Target)
- : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(mbb ? (*mbb)[indexInBB] : 0) {
+ : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb),
+ MI(mbb ? &(*mbb)[indexInBB] : (MachineInstr*)0) {
if (MI) {
MachineOpCode mopCode = MI->getOpcode();
latency = Target.getInstrInfo().hasResultInterlock(mopCode)
// all preceding instructions in the basic block. Use 0 latency again.
//
for (unsigned i=0, N=MBB.size(); i < N; i++) {
- if (MBB[i] == termMvec[first]) // reached the first branch
+ if (&MBB[i] == termMvec[first]) // reached the first branch
break;
- SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
+ SchedGraphNode* fromNode = this->getGraphNodeForInstr(&MBB[i]);
if (fromNode == NULL)
continue; // dummy instruction, e.g., PHI
// the terminator) that also have delay slots, add an outgoing edge
// from the instruction to the instructions in the delay slots.
//
- unsigned d = mii.getNumDelaySlots(MBB[i]->getOpcode());
+ unsigned d = mii.getNumDelaySlots(MBB[i].getOpcode());
assert(i+d < N && "Insufficient delay slots for instruction?");
for (unsigned j=1; j <= d; j++) {
- SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
+ SchedGraphNode* toNode = this->getGraphNodeForInstr(&MBB[i+j]);
assert(toNode && "No node for machine instr in delay slot?");
(void) new SchedGraphEdge(fromNode, toNode,
SchedGraphEdge::CtrlDep,
// Build graph nodes for each VM instruction and gather def/use info.
// Do both those together in a single pass over all machine instructions.
for (unsigned i=0; i < MBB.size(); i++)
- if (!mii.isDummyPhiInstr(MBB[i]->getOpcode())) {
+ if (!mii.isDummyPhiInstr(MBB[i].getOpcode())) {
SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
- noteGraphNodeForInstr(MBB[i], node);
+ noteGraphNodeForInstr(&MBB[i], node);
// Remember all register references and value defs
findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec,
// Then add incoming def-use (SSA) edges for each machine instruction.
for (unsigned i=0, N=MBB.size(); i < N; i++)
- addEdgesForInstruction(*MBB[i], valueToDefVecMap, target);
+ addEdgesForInstruction(MBB[i], valueToDefVecMap, target);
// Then add edges for dependences on machine registers
this->addMachineRegEdges(regToRefVecMap, target);
break;
}
- // find the position of first machine instruction generated by the
- // terminator of this BB
- MachineBasicBlock::iterator MCIt =
- std::find(MBB->begin(), MBB->end(), FirstMIOfTerm);
+ MachineBasicBlock::iterator MCIt = FirstMIOfTerm;
assert(MCIt != MBB->end() && "Start inst of terminator not found");
// iterate over all the machine instructions in BB
for (MachineBasicBlock::const_reverse_iterator MII = MBB.rbegin(),
MIE = MBB.rend(); MII != MIE; ++MII) {
- const MachineInstr *MI = *MII;
+ const MachineInstr *MI = &*MII;
if (DEBUG_LV >= LV_DEBUG_Verbose) {
std::cerr << " *Iterating over machine instr ";
for (MachineBasicBlock::const_reverse_iterator MII = MIVec.rbegin(),
MIE = MIVec.rend(); MII != MIE; ++MII) {
// MI is cur machine inst
- const MachineInstr *MI = *MII;
+ const MachineInstr *MI = &*MII;
MInst2LVSetAI[MI] = SetAI; // record in After Inst map
MachineBasicBlock::const_iterator fwdMII = MII.base(); // ptr to *next* MI
for (unsigned i = 0; i < DS; ++i, ++fwdMII) {
assert(fwdMII != MIVec.end() && "Missing instruction in delay slot?");
- MachineInstr* DelaySlotMI = *fwdMII;
+ const MachineInstr* DelaySlotMI = fwdMII;
if (! TM.getInstrInfo().isNop(DelaySlotMI->getOpcode())) {
set_union(*MInst2LVSetBI[DelaySlotMI], *NewSet);
if (i+1 == DS)
for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
BI != BE; ++BI) {
MachineBasicBlock &miBB = *BI;
- key[miBB[0]] = i;
+ key[&miBB.front()] = i;
i = i+(miBB.size());
}
}
unsigned j = 0;
for(MachineBasicBlock::iterator miI = miBB.begin(), miE = miBB.end();
miI != miE; ++miI, ++j) {
- key[*miI] = j;
+ key[miI] = j;
}
}
}
BI != BE; ++BI, ++bb) {
MachineBasicBlock &miBB = *BI;
writeNumber(bb);
- writeNumber(BBkey[miBB[0]]);
+ writeNumber(BBkey[&miBB.front()]);
writeNumber(miBB.size());
}
}
// iterate over all the machine instructions in BB
for(MachineBasicBlock::iterator MInstIterator = MBB.begin();
MInstIterator != MBB.end(); ++MInstIterator) {
- MachineInstr *MInst = *MInstIterator;
+ MachineInstr *MInst = MInstIterator;
// If the machine instruction is a call/return instruction, add it to
// CallRetInstrList for processing its args, ret value, and ret addr.
// iterate over all the machine instructions in BB
for(MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII){
- const MachineInstr *MI = *MII;
+ const MachineInstr *MI = MII;
if( DEBUG_RA >= RA_DEBUG_LiveRanges) {
std::cerr << " *Iterating over machine instr ";
// iterate over all the machine instructions in BB
for ( ; MII != MBB.end(); ++MII) {
- const MachineInstr *MInst = *MII;
+ const MachineInstr *MInst = MII;
// get the LV set after the instruction
const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
MII = MBB.insert(MII, newMI);
}
-// used by: updateMachineCode (1 time)
-inline void DeleteInstruction(MachineBasicBlock& MBB,
- MachineBasicBlock::iterator& MII) {
- MII = MBB.erase(MII);
-}
-
-// used by: updateMachineCode (1 time)
-inline void SubstituteInPlace(MachineInstr* newMI, MachineBasicBlock& MBB,
- MachineBasicBlock::iterator MII) {
- *MII = newMI;
-}
-
// used by: updateMachineCode (2 times)
inline void PrependInstructions(std::vector<MachineInstr *> &IBef,
MachineBasicBlock& MBB,
MachineBasicBlock::iterator& MII,
const std::string& msg) {
if (!IBef.empty()) {
- MachineInstr* OrigMI = *MII;
+ MachineInstr* OrigMI = MII;
std::vector<MachineInstr *>::iterator AdIt;
for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt) {
if (DEBUG_RA) {
MachineBasicBlock::iterator& MII,
const std::string& msg) {
if (!IAft.empty()) {
- MachineInstr* OrigMI = *MII;
+ MachineInstr* OrigMI = MII;
std::vector<MachineInstr *>::iterator AdIt;
for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
if (DEBUG_RA) {
///
void PhyRegAlloc::updateInstruction(MachineBasicBlock::iterator& MII,
MachineBasicBlock &MBB) {
- MachineInstr* MInst = *MII;
+ MachineInstr* MInst = MII;
unsigned Opcode = MInst->getOpcode();
// Reset tmp stack positions so they can be reused for each machine instr.
MF->getInfo()->popAllTempValues();
// Mark the operands for which regs have been allocated.
- bool instrNeedsSpills = markAllocatedRegs(*MII);
+ bool instrNeedsSpills = markAllocatedRegs(MII);
#ifndef NDEBUG
// Mark that the operands have been updated. Later,
// their assigned registers or insert spill code, as appropriate.
// Also, fix operands of call/return instructions.
for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
- if (! TM.getInstrInfo().isDummyPhiInstr((*MII)->getOpcode()))
+ if (! TM.getInstrInfo().isDummyPhiInstr(MII->getOpcode()))
updateInstruction(MII, MBB);
// Now, move code out of delay slots of branches and returns if needed.
//
// If the annul bit of the branch is set, neither of these is legal!
// If so, we need to handle spill differently but annulling is not yet used.
- for (MachineBasicBlock::iterator MII = MBB.begin();
- MII != MBB.end(); ++MII)
+ for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
if (unsigned delaySlots =
- TM.getInstrInfo().getNumDelaySlots((*MII)->getOpcode())) {
- MachineInstr *MInst = *MII, *DelaySlotMI = *(MII+1);
+ TM.getInstrInfo().getNumDelaySlots(MII->getOpcode())) {
+ MachineBasicBlock::iterator DelaySlotMI = MII; ++DelaySlotMI;
+ assert(DelaySlotMI != MBB.end() && "no instruction for delay slot");
// Check the 2 conditions above:
// (1) Does a branch need instructions added after it?
// (2) O/w does delay slot instr. need instrns before or after?
- bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpcode()) ||
- TM.getInstrInfo().isReturn(MInst->getOpcode()));
+ bool isBranch = (TM.getInstrInfo().isBranch(MII->getOpcode()) ||
+ TM.getInstrInfo().isReturn(MII->getOpcode()));
bool cond1 = (isBranch &&
- AddedInstrMap.count(MInst) &&
- AddedInstrMap[MInst].InstrnsAfter.size() > 0);
+ AddedInstrMap.count(MII) &&
+ AddedInstrMap[MII].InstrnsAfter.size() > 0);
bool cond2 = (AddedInstrMap.count(DelaySlotMI) &&
(AddedInstrMap[DelaySlotMI].InstrnsBefore.size() > 0 ||
AddedInstrMap[DelaySlotMI].InstrnsAfter.size() > 0));
if (cond1 || cond2) {
- assert((MInst->getOpCodeFlags() & AnnulFlag) == 0 &&
+ assert((MII->getOpCodeFlags() & AnnulFlag) == 0 &&
"FIXME: Moving an annulled delay slot instruction!");
assert(delaySlots==1 &&
"InsertBefore does not yet handle >1 delay slots!");
- InsertBefore(DelaySlotMI, MBB, MII); // MII pts back to branch
-
- // In case (1), delete it and don't replace with anything!
- // Otherwise (i.e., case (2) only) replace it with a NOP.
- if (cond1) {
- DeleteInstruction(MBB, ++MII); // MII now points to next inst.
- --MII; // reset MII for ++MII of loop
- }
- else
- SubstituteInPlace(BuildMI(TM.getInstrInfo().getNOPOpCode(),1),
- MBB, MII+1); // replace with NOP
if (DEBUG_RA) {
std::cerr << "\nRegAlloc: Moved instr. with added code: "
<< *DelaySlotMI
- << " out of delay slots of instr: " << *MInst;
+ << " out of delay slots of instr: " << *MII;
+ }
+
+ // move instruction before branch
+ MBB.insert(MII, MBB.remove(DelaySlotMI));
+
+ // On cond1 we are done (we already moved the
+ // instruction out of the delay slot). On cond2 we need
+ // to insert a nop in place of the moved instruction
+ if (cond2) {
+ MBB.insert(MII, BuildMI(TM.getInstrInfo().getNOPOpCode(),1));
}
}
- else
+ else {
// For non-branch instr with delay slots (probably a call), move
// InstrAfter to the instr. in the last delay slot.
- move2DelayedInstr(*MII, *(MII+delaySlots));
- }
+ MachineBasicBlock::iterator tmp = MII;
+ std::advance(tmp, delaySlots);
+ move2DelayedInstr(MII, tmp);
+ }
+ }
// Finally iterate over all instructions in BB and insert before/after
for (MachineBasicBlock::iterator MII=MBB.begin(); MII != MBB.end(); ++MII) {
- MachineInstr *MInst = *MII;
+ MachineInstr *MInst = MII;
// do not process Phis
if (TM.getInstrInfo().isDummyPhiInstr(MInst->getOpcode()))
MachineBasicBlock::iterator& MII,
MachineBasicBlock &MBB,
const unsigned OpNum) {
- MachineInstr *MInst = *MII;
+ MachineInstr *MInst = MII;
const BasicBlock *BB = MBB.getBasicBlock();
assert((! TM.getInstrInfo().isCall(MInst->getOpcode()) || OpNum == 0) &&
// include all live variables before that branch or return -- we don't want to
// trample those! Verify that the set is included in the LV set before MInst.
if (MII != MBB.begin()) {
- MachineInstr *PredMI = *(MII-1);
+ MachineBasicBlock::iterator PredMI = MII;
+ --PredMI;
if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpcode()))
assert(set_difference(LVI->getLiveVarSetBeforeMInst(PredMI), LVSetBef)
.empty() && "Live-var set before branch should be included in "
// Loop over all of the instructions in the basic block...
for (MachineBasicBlock::const_iterator MII = MBB.begin(), MIE = MBB.end();
MII != MIE; ++MII)
- emitMachineInst(*MII);
+ emitMachineInst(MII);
toAsm << "\n"; // Separate BB's with newlines
}
currBB = MBB.getBasicBlock();
BBLocations[currBB] = MCE.getCurrentPCValue();
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
- unsigned binCode = getBinaryCodeForInstr(**I);
+ unsigned binCode = getBinaryCodeForInstr(*I);
if (binCode == (1 << 30)) {
// this is an invalid call: the addr is out of bounds. that means a code
// sequence has already been emitted, and this is a no-op
// Check if this instruction is in a delay slot of its predecessor.
if (BBI != mvec.begin()) {
const TargetInstrInfo& mii = target.getInstrInfo();
- MachineInstr* predMI = *(BBI-1);
+ MachineBasicBlock::iterator predMI = BBI; --predMI;
if (unsigned ndelay = mii.getNumDelaySlots(predMI->getOpcode())) {
// This instruction is in a delay slot of its predecessor, so
// replace it with a nop. By replacing in place, we save having
// to update the I-I maps.
//
assert(ndelay == 1 && "Not yet handling multiple-delay-slot targets");
- (*BBI)->replace(mii.getNOPOpCode(), 0);
+ BBI->replace(mii.getNOPOpCode(), 0);
return;
}
}
RemoveUselessCopies(MachineBasicBlock& mvec,
MachineBasicBlock::iterator& BBI,
const TargetMachine& target) {
- if (IsUselessCopy(target, *BBI)) {
+ if (IsUselessCopy(target, BBI)) {
DeleteInstruction(mvec, BBI, target);
return true;
}
assert(MBB && "MachineBasicBlock object not found for specified block!");
MachineBasicBlock &mvec = *MBB;
- // Iterate over all machine instructions in the BB
- // Use a reverse iterator to allow deletion of MI or any instruction after it.
- // Insertions or deletions *before* MI are not safe.
- //
- for (MachineBasicBlock::reverse_iterator RI=mvec.rbegin(),
- RE=mvec.rend(); RI != RE; ) {
- MachineBasicBlock::iterator BBI = RI.base()-1; // save before incr
- ++RI; // pre-increment to delete MI or after it
- visit(mvec, BBI);
- }
+ for (MachineBasicBlock::iterator I = mvec.begin(), E = mvec.end(); I != E; )
+ visit(mvec, I++);
return true;
}
unsigned numNOPs = 0;
while (termMvec.back()->getOpcode() == V9::NOP)
{
- assert( termMvec.back() == MBB.back());
- delete MBB.pop_back();
+ assert( termMvec.back() == &MBB.back());
termMvec.pop_back();
+ MBB.erase(&MBB.back());
++numNOPs;
}
- assert(termMvec.back() == MBB.back());
+ assert(termMvec.back() == &MBB.back());
// Check that we found the right number of NOPs and have the right
// number of instructions to replace them.
// Emit an fxch to update the runtime processors version of the state
MachineInstr *MI = BuildMI(X86::FXCH, 1).addReg(STReg);
- I = 1+MBB->insert(I, MI);
+ MBB->insert(I, MI);
NumFXCH++;
}
}
pushReg(AsReg); // New register on top of stack
MachineInstr *MI = BuildMI(X86::FLDrr, 1).addReg(STReg);
- I = 1+MBB->insert(I, MI);
+ MBB->insert(I, MI);
}
// popStackAfter - Pop the current value off of the top of the FP stack
MBB = &BB;
for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
unsigned Flags = TII.get(MI->getOpcode()).TSFlags;
if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
continue; // Efficiently ignore non-fp insts!
- MachineInstr *PrevMI = I == BB.begin() ? 0 : *(I-1);
+ MachineInstr *PrevMI = 0;
+ if (I != BB.begin()) {
+ MachineBasicBlock::iterator tmp = I;
+ --tmp;
+ PrevMI = tmp;
+ }
++NumFP; // Keep track of # of pseudo instrs
DEBUG(std::cerr << "\nFPInst:\t";
}
// Print out all of the instructions expanded to if -debug
- DEBUG(if (*I == PrevMI) {
+ DEBUG(if (&*I == PrevMI) {
std::cerr<< "Just deleted pseudo instruction\n";
} else {
MachineBasicBlock::iterator Start = I;
// Rewind to first instruction newly inserted.
- while (Start != BB.begin() && *(Start-1) != PrevMI) --Start;
+ while (Start != BB.begin() &&
+ --Start != MachineBasicBlock::iterator(PrevMI));
+ ++Start;
std::cerr << "Inserted instructions:\n\t";
- (*Start)->print(std::cerr, MF.getTarget());
- while (++Start != I+1);
+ Start->print(std::cerr, MF.getTarget());
+ while (++Start != I); ++Start;
}
dumpStack();
);
RegMap[Stack[--StackTop]] = ~0; // Update state
// Check to see if there is a popping version of this instruction...
- int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), (*I)->getOpcode());
+ int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode());
if (Opcode != -1) {
- (*I)->setOpcode(Opcode);
+ I->setOpcode(Opcode);
if (Opcode == X86::FUCOMPPr)
- (*I)->RemoveOperand(0);
+ I->RemoveOperand(0);
} else { // Insert an explicit pop
MachineInstr *MI = BuildMI(X86::FSTPrr, 1).addReg(X86::ST0);
- I = MBB->insert(I+1, MI);
+ I = MBB->insert(++I, MI);
}
}
/// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
///
void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
unsigned DestReg = getFPReg(MI->getOperand(0));
MI->RemoveOperand(0); // Remove the explicit ST(0) operand
/// handleOneArgFP - fst <mem>, ST(0)
///
void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
assert((MI->getNumOperands() == 5 || MI->getNumOperands() == 1) &&
"Can only handle fst* & ftst instructions!");
/// handleOneArgFPRW - fchs - ST(0) = -ST(0)
///
void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
assert(MI->getNumOperands() == 2 && "Can only handle fst* instructions!");
// Is this the last use of the source register?
void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
unsigned NumOperands = MI->getNumOperands();
assert(NumOperands == 3 ||
unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
// Replace the old instruction with a new instruction
- *I = BuildMI(Opcode, 1).addReg(getSTReg(NotTOS));
+ MBB->remove(I);
+ I = MBB->insert(I, BuildMI(Opcode, 1).addReg(getSTReg(NotTOS)));
// If both operands are killed, pop one off of the stack in addition to
// overwriting the other one.
Stack[--StackTop] = ~0;
MachineInstr *MI = BuildMI(X86::FSTPrr, 1).addReg(STReg);
- I = MBB->insert(I+1, MI);
+ I = MBB->insert(++I, MI);
}
}
}
/// instructions.
///
void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
switch (MI->getOpcode()) {
default: assert(0 && "Unknown SpecialFP instruction!");
case X86::FpGETRESULT: // Appears immediately after a call returning FP type!
}
}
- I = MBB->erase(I)-1; // Remove the pseudo instruction
- delete MI;
+ I = MBB->erase(I); // Remove the pseudo instruction
+ --I;
}
/// instruction at as well as a basic block. This is the version for when you
/// have a destination register in mind.
inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
- MachineBasicBlock::iterator &I,
+ MachineBasicBlock::iterator I,
int Opcode, unsigned NumOperands,
unsigned DestReg) {
- assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
- I = MBB->insert(I, MI)+1;
+ MBB->insert(I, MI);
return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
}
/// BMI - A special BuildMI variant that takes an iterator to insert the
/// instruction at as well as a basic block.
inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
- MachineBasicBlock::iterator &I,
+ MachineBasicBlock::iterator I,
int Opcode, unsigned NumOperands) {
- assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
- I = MBB->insert(I, MI)+1;
+ MBB->insert(I, MI);
return MachineInstrBuilder(MI);
}
MachineBasicBlock *MBB = MBBMap[I];
// Loop over all of the PHI nodes in the LLVM basic block...
- unsigned NumPHIs = 0;
+ MachineInstr* instr = MBB->begin();
for (BasicBlock::const_iterator I = BB->begin();
PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
// Create a new machine instr PHI node, and insert it.
unsigned PHIReg = getReg(*PN);
MachineInstr *PhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg);
- MBB->insert(MBB->begin()+NumPHIs++, PhiMI);
+ MBB->insert(instr, PhiMI);
MachineInstr *LongPhiMI = 0;
if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) {
LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
- MBB->insert(MBB->begin()+NumPHIs++, LongPhiMI);
+ MBB->insert(instr, LongPhiMI);
}
// PHIValues - Map of blocks to incoming virtual registers. We use this
MachineBasicBlock::iterator PI = PredMBB->begin();
// Skip over any PHI nodes though!
- while (PI != PredMBB->end() && (*PI)->getOpcode() == X86::PHI)
+ while (PI != PredMBB->end() && PI->getOpcode() == X86::PHI)
++PI;
ValReg = getReg(Val, PredMBB, PI);
bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I) {
- MachineInstr *MI = *I;
- MachineInstr *Next = (I+1 != MBB.end()) ? *(I+1) : 0;
+ assert(I != MBB.end());
+ MachineBasicBlock::iterator NextI = I; ++NextI;
+
+ MachineInstr *MI = I;
+ MachineInstr *Next = (NextI != MBB.end()) ? &*NextI : (MachineInstr*)0;
unsigned Size = 0;
switch (MI->getOpcode()) {
case X86::MOVrr8:
case X86::MOVrr32: // Destroy X = X copies...
if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
I = MBB.erase(I);
- delete MI;
return true;
}
return false;
}
unsigned R0 = MI->getOperand(0).getReg();
unsigned R1 = MI->getOperand(1).getReg();
- *I = BuildMI(Opcode, 2, R0).addReg(R1).addZImm((char)Val);
- delete MI;
+ I = MBB.insert(MBB.erase(I),
+ BuildMI(Opcode, 2, R0).addReg(R1).addZImm((char)Val));
return true;
}
}
case X86::XORri32: Opcode = X86::XORri32b; break;
}
unsigned R0 = MI->getOperand(0).getReg();
- *I = BuildMI(Opcode, 1, R0, MOTy::UseAndDef).addZImm((char)Val);
- delete MI;
+ I = MBB.insert(MBB.erase(I),
+ BuildMI(Opcode, 1, R0, MOTy::UseAndDef).addZImm((char)Val));
return true;
}
}
if (Val == 0) { // mov EAX, 0 -> xor EAX, EAX
static const unsigned Opcode[] ={X86::XORrr8,X86::XORrr16,X86::XORrr32};
unsigned Reg = MI->getOperand(0).getReg();
- *I = BuildMI(Opcode[Size], 2, Reg).addReg(Reg).addReg(Reg);
- delete MI;
+ I = MBB.insert(MBB.erase(I),
+ BuildMI(Opcode[Size], 2, Reg).addReg(Reg).addReg(Reg));
return true;
} else if (Val == -1) { // mov EAX, -1 -> or EAX, -1
// TODO: 'or Reg, -1' has a smaller encoding than 'mov Reg, -1'
if (Next->getOpcode() == X86::BSWAPr32 &&
MI->getOperand(0).getReg() == Next->getOperand(0).getReg()) {
I = MBB.erase(MBB.erase(I));
- delete MI;
- delete Next;
return true;
}
return false;
virtual bool runOnMachineFunction(MachineFunction &MF) {
for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI!=E; ++BI)
for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); ++I) {
- MachineInstr *MI = *I;
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI->getOperand(i);
+ for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = I->getOperand(i);
if (MO.isRegister() && MO.isDef() && !MO.isUse() &&
MRegisterInfo::isVirtualRegister(MO.getReg()))
- setDefinition(MO.getReg(), MI);
+ setDefinition(MO.getReg(), I);
}
}
return false;
bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I) {
- MachineInstr *MI = *I;
- MachineInstr *Next = (I+1 != MBB.end()) ? *(I+1) : 0;
+ MachineBasicBlock::iterator NextI = I; ++NextI;
+
+ MachineInstr *MI = I;
+ MachineInstr *Next = (NextI != MBB.end()) ? &*NextI : (MachineInstr*)0;
bool Changed = false;
II != E; ++II) {
// Print the assembly for the instruction.
O << "\t";
- printMachineInstruction(*II);
+ printMachineInstruction(II);
}
}
II != E; ++II) {
// Print the assembly for the instruction.
O << "\t";
- printMachineInstruction(*II);
+ printMachineInstruction(II);
}
}
bool X86TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
MachineCodeEmitter &MCE) {
PM.add(new Emitter(MCE));
- // Delete machine code for this function
- PM.add(createMachineCodeDeleter());
return false;
}
BasicBlockAddrs[MBB.getBasicBlock()] = Addr;
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
- emitInstruction(**I);
+ emitInstruction(*I);
}
// Emit an fxch to update the runtime processors version of the state
MachineInstr *MI = BuildMI(X86::FXCH, 1).addReg(STReg);
- I = 1+MBB->insert(I, MI);
+ MBB->insert(I, MI);
NumFXCH++;
}
}
pushReg(AsReg); // New register on top of stack
MachineInstr *MI = BuildMI(X86::FLDrr, 1).addReg(STReg);
- I = 1+MBB->insert(I, MI);
+ MBB->insert(I, MI);
}
// popStackAfter - Pop the current value off of the top of the FP stack
MBB = &BB;
for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
unsigned Flags = TII.get(MI->getOpcode()).TSFlags;
if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
continue; // Efficiently ignore non-fp insts!
- MachineInstr *PrevMI = I == BB.begin() ? 0 : *(I-1);
+ MachineInstr *PrevMI = 0;
+ if (I != BB.begin()) {
+ MachineBasicBlock::iterator tmp = I;
+ --tmp;
+ PrevMI = tmp;
+ }
++NumFP; // Keep track of # of pseudo instrs
DEBUG(std::cerr << "\nFPInst:\t";
}
// Print out all of the instructions expanded to if -debug
- DEBUG(if (*I == PrevMI) {
+ DEBUG(if (&*I == PrevMI) {
std::cerr<< "Just deleted pseudo instruction\n";
} else {
MachineBasicBlock::iterator Start = I;
// Rewind to first instruction newly inserted.
- while (Start != BB.begin() && *(Start-1) != PrevMI) --Start;
+ while (Start != BB.begin() &&
+ --Start != MachineBasicBlock::iterator(PrevMI));
+ ++Start;
std::cerr << "Inserted instructions:\n\t";
- (*Start)->print(std::cerr, MF.getTarget());
- while (++Start != I+1);
+ Start->print(std::cerr, MF.getTarget());
+ while (++Start != I); ++Start;
}
dumpStack();
);
RegMap[Stack[--StackTop]] = ~0; // Update state
// Check to see if there is a popping version of this instruction...
- int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), (*I)->getOpcode());
+ int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode());
if (Opcode != -1) {
- (*I)->setOpcode(Opcode);
+ I->setOpcode(Opcode);
if (Opcode == X86::FUCOMPPr)
- (*I)->RemoveOperand(0);
+ I->RemoveOperand(0);
} else { // Insert an explicit pop
MachineInstr *MI = BuildMI(X86::FSTPrr, 1).addReg(X86::ST0);
- I = MBB->insert(I+1, MI);
+ I = MBB->insert(++I, MI);
}
}
/// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
///
void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
unsigned DestReg = getFPReg(MI->getOperand(0));
MI->RemoveOperand(0); // Remove the explicit ST(0) operand
/// handleOneArgFP - fst <mem>, ST(0)
///
void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
assert((MI->getNumOperands() == 5 || MI->getNumOperands() == 1) &&
"Can only handle fst* & ftst instructions!");
/// handleOneArgFPRW - fchs - ST(0) = -ST(0)
///
void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
assert(MI->getNumOperands() == 2 && "Can only handle fst* instructions!");
// Is this the last use of the source register?
void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
unsigned NumOperands = MI->getNumOperands();
assert(NumOperands == 3 ||
unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
// Replace the old instruction with a new instruction
- *I = BuildMI(Opcode, 1).addReg(getSTReg(NotTOS));
+ MBB->remove(I);
+ I = MBB->insert(I, BuildMI(Opcode, 1).addReg(getSTReg(NotTOS)));
// If both operands are killed, pop one off of the stack in addition to
// overwriting the other one.
Stack[--StackTop] = ~0;
MachineInstr *MI = BuildMI(X86::FSTPrr, 1).addReg(STReg);
- I = MBB->insert(I+1, MI);
+ I = MBB->insert(++I, MI);
}
}
}
/// instructions.
///
void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
switch (MI->getOpcode()) {
default: assert(0 && "Unknown SpecialFP instruction!");
case X86::FpGETRESULT: // Appears immediately after a call returning FP type!
}
}
- I = MBB->erase(I)-1; // Remove the pseudo instruction
- delete MI;
+ I = MBB->erase(I); // Remove the pseudo instruction
+ --I;
}
/// instruction at as well as a basic block. This is the version for when you
/// have a destination register in mind.
inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
- MachineBasicBlock::iterator &I,
+ MachineBasicBlock::iterator I,
int Opcode, unsigned NumOperands,
unsigned DestReg) {
- assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
- I = MBB->insert(I, MI)+1;
+ MBB->insert(I, MI);
return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
}
/// BMI - A special BuildMI variant that takes an iterator to insert the
/// instruction at as well as a basic block.
inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
- MachineBasicBlock::iterator &I,
+ MachineBasicBlock::iterator I,
int Opcode, unsigned NumOperands) {
- assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
- I = MBB->insert(I, MI)+1;
+ MBB->insert(I, MI);
return MachineInstrBuilder(MI);
}
MachineBasicBlock *MBB = MBBMap[I];
// Loop over all of the PHI nodes in the LLVM basic block...
- unsigned NumPHIs = 0;
+ MachineInstr* instr = MBB->begin();
for (BasicBlock::const_iterator I = BB->begin();
PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
// Create a new machine instr PHI node, and insert it.
unsigned PHIReg = getReg(*PN);
MachineInstr *PhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg);
- MBB->insert(MBB->begin()+NumPHIs++, PhiMI);
+ MBB->insert(instr, PhiMI);
MachineInstr *LongPhiMI = 0;
if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) {
LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
- MBB->insert(MBB->begin()+NumPHIs++, LongPhiMI);
+ MBB->insert(instr, LongPhiMI);
}
// PHIValues - Map of blocks to incoming virtual registers. We use this
MachineBasicBlock::iterator PI = PredMBB->begin();
// Skip over any PHI nodes though!
- while (PI != PredMBB->end() && (*PI)->getOpcode() == X86::PHI)
+ while (PI != PredMBB->end() && PI->getOpcode() == X86::PHI)
++PI;
ValReg = getReg(Val, PredMBB, PI);
bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I) {
- MachineInstr *MI = *I;
- MachineInstr *Next = (I+1 != MBB.end()) ? *(I+1) : 0;
+ assert(I != MBB.end());
+ MachineBasicBlock::iterator NextI = I; ++NextI;
+
+ MachineInstr *MI = I;
+ MachineInstr *Next = (NextI != MBB.end()) ? &*NextI : (MachineInstr*)0;
unsigned Size = 0;
switch (MI->getOpcode()) {
case X86::MOVrr8:
case X86::MOVrr32: // Destroy X = X copies...
if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
I = MBB.erase(I);
- delete MI;
return true;
}
return false;
}
unsigned R0 = MI->getOperand(0).getReg();
unsigned R1 = MI->getOperand(1).getReg();
- *I = BuildMI(Opcode, 2, R0).addReg(R1).addZImm((char)Val);
- delete MI;
+ I = MBB.insert(MBB.erase(I),
+ BuildMI(Opcode, 2, R0).addReg(R1).addZImm((char)Val));
return true;
}
}
case X86::XORri32: Opcode = X86::XORri32b; break;
}
unsigned R0 = MI->getOperand(0).getReg();
- *I = BuildMI(Opcode, 1, R0, MOTy::UseAndDef).addZImm((char)Val);
- delete MI;
+ I = MBB.insert(MBB.erase(I),
+ BuildMI(Opcode, 1, R0, MOTy::UseAndDef).addZImm((char)Val));
return true;
}
}
if (Val == 0) { // mov EAX, 0 -> xor EAX, EAX
static const unsigned Opcode[] ={X86::XORrr8,X86::XORrr16,X86::XORrr32};
unsigned Reg = MI->getOperand(0).getReg();
- *I = BuildMI(Opcode[Size], 2, Reg).addReg(Reg).addReg(Reg);
- delete MI;
+ I = MBB.insert(MBB.erase(I),
+ BuildMI(Opcode[Size], 2, Reg).addReg(Reg).addReg(Reg));
return true;
} else if (Val == -1) { // mov EAX, -1 -> or EAX, -1
// TODO: 'or Reg, -1' has a smaller encoding than 'mov Reg, -1'
if (Next->getOpcode() == X86::BSWAPr32 &&
MI->getOperand(0).getReg() == Next->getOperand(0).getReg()) {
I = MBB.erase(MBB.erase(I));
- delete MI;
- delete Next;
return true;
}
return false;
virtual bool runOnMachineFunction(MachineFunction &MF) {
for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI!=E; ++BI)
for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); ++I) {
- MachineInstr *MI = *I;
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI->getOperand(i);
+ for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = I->getOperand(i);
if (MO.isRegister() && MO.isDef() && !MO.isUse() &&
MRegisterInfo::isVirtualRegister(MO.getReg()))
- setDefinition(MO.getReg(), MI);
+ setDefinition(MO.getReg(), I);
}
}
return false;
bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I) {
- MachineInstr *MI = *I;
- MachineInstr *Next = (I+1 != MBB.end()) ? *(I+1) : 0;
+ MachineBasicBlock::iterator NextI = I; ++NextI;
+
+ MachineInstr *MI = I;
+ MachineInstr *Next = (NextI != MBB.end()) ? &*NextI : (MachineInstr*)0;
bool Changed = false;
}
int X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
+ MachineInstr* MI,
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const {
static const unsigned Opcode[] =
{ X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTPr80 };
- MachineInstr *MI = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
+ MachineInstr *I = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
FrameIdx).addReg(SrcReg);
- MBBI = MBB.insert(MBBI, MI)+1;
+ MBB.insert(MI, I);
return 1;
}
int X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
+ MachineInstr* MI,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const{
static const unsigned Opcode[] =
{ X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr80 };
- MachineInstr *MI = addFrameReference(BuildMI(Opcode[getIdx(RC)], 4, DestReg),
- FrameIdx);
- MBBI = MBB.insert(MBBI, MI)+1;
+ unsigned OC = Opcode[getIdx(RC)];
+ MBB.insert(MI, addFrameReference(BuildMI(OC, 4, DestReg), FrameIdx));
return 1;
}
int X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
+ MachineInstr* MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
static const unsigned Opcode[] =
{ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV };
- MachineInstr *MI = BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg);
- MBBI = MBB.insert(MBBI, MI)+1;
+ MBB.insert(MI, BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg));
return 1;
}
int X86RegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &I) const {
- MachineInstr *New = 0, *Old = *I;;
+ MachineInstr* I) const {
+ MachineInstr *New = 0, *Old = I;
if (hasFP(MF)) {
// If we have a frame pointer, turn the adjcallstackup instruction into a
// 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
}
if (New) {
- *I = New; // Replace the pseudo instruction with a new instruction...
- delete Old;
+ // Replace the pseudo instruction with a new instruction...
+ MBB.insert(MBB.erase(I), New);
return 0;
} else {
- I = MBB.erase(I);// Just delete the pseudo instruction...
- delete Old;
+ MBB.erase(I);
return -1;
}
}
int X86RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
- MachineBasicBlock::iterator &II) const {
+ MachineInstr* II) const {
unsigned i = 0;
- MachineInstr &MI = **II;
+ MachineInstr &MI = *II;
while (!MI.getOperand(i).isFrameIndex()) {
++i;
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
if (NumBytes) { // adjust stack pointer: ESP -= numbytes
MI= BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
- MBBI = MBB.insert(MBBI, MI)+1;
+ MBB.insert(MBBI, MI);
}
// Save EBP into the appropriate stack slot...
MI = addRegOffset(BuildMI(X86::MOVrm32, 5), // mov [ESP-<offset>], EBP
X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
- MBBI = MBB.insert(MBBI, MI)+1;
+ MBB.insert(MBBI, MI);
// Update EBP with the new base value...
if (NumBytes == 0) // mov EBP, ESP
else // lea EBP, [ESP+StackSize]
MI = addRegOffset(BuildMI(X86::LEAr32, 5, X86::EBP), X86::ESP, NumBytes);
- MBBI = MBB.insert(MBBI, MI)+1;
+ MBB.insert(MBBI, MI);
} else {
// When we have no frame pointer, we reserve argument space for call sites
MachineBasicBlock &MBB) const {
unsigned oldSize = MBB.size();
const MachineFrameInfo *MFI = MF.getFrameInfo();
- MachineBasicBlock::iterator MBBI = MBB.end()-1;
+ MachineBasicBlock::iterator MBBI = MBB.end(); --MBBI;
MachineInstr *MI;
- assert((*MBBI)->getOpcode() == X86::RET &&
+ assert(MBBI->getOpcode() == X86::RET &&
"Can only insert epilog into returning blocks");
if (hasFP(MF)) {
// mov ESP, EBP
MI = BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP);
- MBBI = 1+MBB.insert(MBBI, MI);
+ MBB.insert(MBBI, MI);
// mov EBP, [ESP-<offset>]
MI = addRegOffset(BuildMI(X86::MOVmr32, 5, X86::EBP), X86::ESP, EBPOffset);
- MBBI = 1+MBB.insert(MBBI, MI);
+ MBB.insert(MBBI, MI);
} else {
// Get the number of bytes allocated from the FrameInfo...
unsigned NumBytes = MFI->getStackSize();
if (NumBytes) { // adjust stack pointer back: ESP += numbytes
MI =BuildMI(X86::ADDri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
- MBBI = 1+MBB.insert(MBBI, MI);
+ MBB.insert(MBBI, MI);
}
}
return MBB.size() - oldSize;
/// Code Generation virtual methods...
int storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
+ MachineInstr* MI,
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const;
int loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
+ MachineInstr* MI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const;
- int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
+ int copyRegToReg(MachineBasicBlock &MBB,
+ MachineInstr* MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
int eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &I) const;
+ MachineInstr* MI) const;
int eliminateFrameIndex(MachineFunction &MF,
- MachineBasicBlock::iterator &II) const;
+ MachineInstr* MI) const;
int processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
if (!DisableOutput)
PM.add(createX86CodePrinterPass(Out, *this));
- // Delete machine code for this function
- PM.add(createMachineCodeDeleter());
-
return false; // success!
}
projects / oota-llvm.git / commitdiff