Change mips16 delay slot jumps to non delay slot forms by default.

We will make them delay slot forms if there is something that can be
placed in the delay slot during a separate pass. Mips16 extended instructions
cannot be placed in delay slots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166990 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/Mips16InstrInfo.cpp b/lib/Target/Mips/Mips16InstrInfo.cpp
index 5e33fed0cc975061e8e4f4965b3d1dc3819f52d8..fa0876a4ebec7d15278b7994e933aca5df4c4e56 100644 (file)
--- a/lib/Target/Mips/Mips16InstrInfo.cpp
+++ b/lib/Target/Mips/Mips16InstrInfo.cpp
@@ -126,7 +126,7 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
   default:
     return false;
   case Mips::RetRA16:
-    ExpandRetRA16(MBB, MI, Mips::JrRa16);
+    ExpandRetRA16(MBB, MI, Mips::JrcRa16);
     break;
   }
 

diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td
index 2740a1d83a86fdf87dbfef8488fdd26b9fdb742f..5f8af05f0c515d80c768f38b06b31750ff95a0df 100644 (file)
--- a/lib/Target/Mips/Mips16InstrInfo.td
+++ b/lib/Target/Mips/Mips16InstrInfo.td
@@ -515,6 +515,13 @@ def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
   let isBarrier=1;
 }
 
+def JrcRa16: FRR16_JALRC_RA_only_ins<0, 0, "jrc", IIAlu> {
+  let isBranch = 1;
+  let isIndirectBranch = 1;
+  let isTerminator=1;
+  let isBarrier=1;
+}
+
 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
   let isBranch = 1;
   let isIndirectBranch = 1;
@@ -1011,10 +1018,10 @@ def: Mips16Pat<
 
 
 // Jump and Link (Call)
-let isCall=1, hasDelaySlot=1 in
+let isCall=1, hasDelaySlot=0 in
 def JumpLinkReg16:
   FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
-              "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
+              "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
 
 // Mips16 pseudos
 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,

diff --git a/test/CodeGen/Mips/helloworld.ll b/test/CodeGen/Mips/helloworld.ll
index bee93accd4284a916d3455e5da1bb742a38f3e1d..aee58b650e7ac044af4bbb78b0356eae20710bc7 100644 (file)
--- a/test/CodeGen/Mips/helloworld.ll
+++ b/test/CodeGen/Mips/helloworld.ll
@@ -24,10 +24,10 @@ entry:
 ; C1:  addiu   ${{[0-9]+}}, %lo($.str)
 ; C2:  move    $25, ${{[0-9]+}}
 ; C1:  move    $gp, ${{[0-9]+}}
-; C1:  jalr    ${{[0-9]+}}
+; C1:  jalrc   ${{[0-9]+}}
 ; SR:  restore         $ra, [[FS]]
 ; PE:  li      $2, 0
-; PE:  jr      $ra
+; PE:  jrc     $ra
 
 }
 

diff --git a/test/CodeGen/Mips/null.ll b/test/CodeGen/Mips/null.ll
index 7beae99c45574d7537a763d6e4429c12c592d52e..00c66a9928f620da66e467e2e11295cca5ff3d2a 100644 (file)
--- a/test/CodeGen/Mips/null.ll
+++ b/test/CodeGen/Mips/null.ll
@@ -8,6 +8,6 @@ entry:
 ; 16:  .set    mips16                  # @main
 
 
-; 16:  jr      $ra
+; 16:  jrc     $ra
 
 }