Allow more cross-rc coalescing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98048 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/MachineCSE.cpp b/lib/CodeGen/MachineCSE.cpp
index 68407c88d8ee3ae62875c6f376b7fd235ba64dd8..e65d3bcaf2083da8f9d19ba716bd51cffa4b2c5b 100644 (file)
--- a/lib/CodeGen/MachineCSE.cpp
+++ b/lib/CodeGen/MachineCSE.cpp
@@ -93,16 +93,19 @@ bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
     if (TII->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
         TargetRegisterInfo::isVirtualRegister(SrcReg) &&
         !SrcSubIdx && !DstSubIdx) {
-      const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
-      const TargetRegisterClass *RC  = MRI->getRegClass(Reg);
-      if (SRC == RC || RC->hasSubClass(SRC)) {
-        DEBUG(dbgs() << "Coalescing: " << *DefMI);
-        DEBUG(dbgs() << "*** to: " << *MI);
-        MO.setReg(SrcReg);
-        DefMI->eraseFromParent();
-        ++NumCoalesces;
-        Changed = true;
-      }
+      const TargetRegisterClass *SRC   = MRI->getRegClass(SrcReg);
+      const TargetRegisterClass *RC    = MRI->getRegClass(Reg);
+      const TargetRegisterClass *NewRC = getCommonSubClass(RC, SRC);
+      if (!NewRC)
+        continue;
+      DEBUG(dbgs() << "Coalescing: " << *DefMI);
+      DEBUG(dbgs() << "*** to: " << *MI);
+      MO.setReg(SrcReg);
+      if (NewRC != SRC)
+        MRI->setRegClass(SrcReg, NewRC);
+      DefMI->eraseFromParent();
+      ++NumCoalesces;
+      Changed = true;
     }
   }