/// SSE 1 Only
// Aliases for intrinsics
+let isAsmParserOnly = 1, Pattern = []<dag> in {
+defm Int_VCVTTSS2SI : sse12_cvt_sint_3addr<0x2C, VR128, GR32,
+ int_x86_sse_cvttss2si, f32mem, load,
+ "cvttss2si\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS;
+defm Int_VCVTTSD2SI : sse12_cvt_sint_3addr<0x2C, VR128, GR32,
+ int_x86_sse2_cvttsd2si, f128mem, load,
+ "cvttss2si\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD;
+}
defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
f32mem, load, "cvttss2si\t{$src, $dst|$dst, $src}">,
XS;
f128mem, load, "cvttss2si\t{$src, $dst|$dst, $src}">,
XD;
+let isAsmParserOnly = 1, Pattern = []<dag> in {
+defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
+ "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
+defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load,
+ "cvtdq2ps\t{$src, $dst|$dst, $src}",
+ SSEPackedSingle>, TB, VEX;
+}
let Pattern = []<dag> in {
defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
"cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
// CHECK: encoding: [0xc5,0xe8,0x12,0xd9]
vmovhlps %xmm1, %xmm2, %xmm3
+// CHECK: vcvtss2sil %xmm1, %eax
+// CHECK: encoding: [0xc5,0xfa,0x2d,0xc1]
+ vcvtss2si %xmm1, %eax
+
+// CHECK: vcvtss2sil (%eax), %ebx
+// CHECK: encoding: [0xc5,0xfa,0x2d,0x18]
+ vcvtss2si (%eax), %ebx
+
+// CHECK: vcvtdq2ps %xmm5, %xmm6
+// CHECK: encoding: [0xc5,0xf8,0x5b,0xf5]
+ vcvtdq2ps %xmm5, %xmm6
+
+// CHECK: vcvtdq2ps (%eax), %xmm6
+// CHECK: encoding: [0xc5,0xf8,0x5b,0x30]
+ vcvtdq2ps (%eax), %xmm6
+
// CHECK: encoding: [0xc4,0x41,0x18,0x12,0xeb]
vmovhlps %xmm11, %xmm12, %xmm13
+// CHECK: vcvtss2sil %xmm11, %eax
+// CHECK: encoding: [0xc4,0xc1,0x7a,0x2d,0xc3]
+ vcvtss2si %xmm11, %eax
+
+// CHECK: vcvtss2sil (%rax), %ebx
+// CHECK: encoding: [0xc5,0xfa,0x2d,0x18]
+ vcvtss2si (%rax), %ebx
+
+// CHECK: vcvtdq2ps %xmm10, %xmm12
+// CHECK: encoding: [0xc4,0x41,0x78,0x5b,0xe2]
+ vcvtdq2ps %xmm10, %xmm12
+
+// CHECK: vcvtdq2ps (%rax), %xmm12
+// CHECK: encoding: [0xc5,0x78,0x5b,0x20]
+ vcvtdq2ps (%rax), %xmm12