handle case where a register class is specified

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112842 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/TargetRegisterInfo.cpp b/lib/Target/TargetRegisterInfo.cpp
index cdbe51fbdd92d748f751a9e1944e1e520a87e7d5..6addbab851ef041f41bc1896daf599be1b7c9f60 100644 (file)
--- a/lib/Target/TargetRegisterInfo.cpp
+++ b/lib/Target/TargetRegisterInfo.cpp
@@ -74,12 +74,11 @@ BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
   BitVector Allocatable(NumRegs);
   if (RC) {
     getAllocatableSetForRC(MF, RC, Allocatable);
-    return Allocatable;
-  }
-
-  for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
+  } else {
+    for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
          E = regclass_end(); I != E; ++I)
-    getAllocatableSetForRC(MF, *I, Allocatable);
+      getAllocatableSetForRC(MF, *I, Allocatable);
+  }
 
   // Mask out the reserved registers
   BitVector Reserved = getReservedRegs(MF);