[FastIsel][AArch64] Fix previous commit r214844 (Don't perform sign-/zero-extension...

The original code would fail for unsupported value types like i1, i8, and i16.
This fix changes the code to only create a sub-register copy for i64 value types
and all other types (i1/i8/i16/i32) just use the source register without any
modifications.

getRegClassFor() is now guarded by the i64 value type check, that guarantees
that we always request a register for a valid value type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214848 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64FastISel.cpp b/lib/Target/AArch64/AArch64FastISel.cpp
index 7aebf4be042bcdfdf0e4207459b7d70b28cf9725..7919e47f5df78546d31876d4635e956a29c33263 100644 (file)
--- a/lib/Target/AArch64/AArch64FastISel.cpp
+++ b/lib/Target/AArch64/AArch64FastISel.cpp
@@ -2443,17 +2443,15 @@ bool AArch64FastISel::SelectIntExt(const Instruction *I) {
   // Check if it is an argument and if it is already zero/sign-extended.
   if (const auto *Arg = dyn_cast<Argument>(Src)) {
     if ((isZExt && Arg->hasZExtAttr()) || (!isZExt && Arg->hasSExtAttr())) {
-      ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
-      if (DestVT == MVT::i64)
+      if (DestVT == MVT::i64) {
+        ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
         BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
                 TII.get(AArch64::SUBREG_TO_REG), ResultReg)
           .addImm(0)
           .addReg(SrcReg)
           .addImm(AArch64::sub_32);
-      else
-        BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
-                TII.get(TargetOpcode::COPY), ResultReg)
-          .addReg(SrcReg);
+      } else
+        ResultReg = SrcReg;
     }
   }