Make register scavenging happy by not using a reg (CR0) that isn't defined

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47045 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 616c0e7b4c82e8cea64a428d52bcd7103099c110..212268ce96cd157751bcd44b207cc7b783224549 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -293,7 +293,7 @@ def memrix : Operand<iPTR> {   // memri where the imm is shifted 2 bits.
 // PowerPC Predicate operand.  20 = (0<<5)|20 = always, CR0 is a dummy reg
 // that doesn't matter.
 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
-                                     (ops (i32 20), CR0)> {
+                                     (ops (i32 20), (i32 zero_reg))> {
   let PrintMethod = "printPredicateOperand";
 }