Add Cortex-A53 and Cortex-A57 cores to the AArch64 backend

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201305 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64.td b/lib/Target/AArch64/AArch64.td
index 6139d147a617c1b499aef15ea5cc5e11ac407535..bde09cd5c2991cc0c2c4270dd08044bcde5a742e 100644 (file)
--- a/lib/Target/AArch64/AArch64.td
+++ b/lib/Target/AArch64/AArch64.td
@@ -36,8 +36,19 @@ def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
 
 include "AArch64Schedule.td"
 
+class ProcNoItin<string Name, list<SubtargetFeature> Features>
+ : Processor<Name, NoItineraries, Features>;
+
 def : Processor<"generic", GenericItineraries, [FeatureFPARMv8]>;
 
+def : ProcNoItin<"cortex-a53",      [FeatureFPARMv8,
+                                    FeatureNEON,
+                                    FeatureCrypto]>;
+
+def : ProcNoItin<"cortex-a57",      [FeatureFPARMv8,
+                                    FeatureNEON,
+                                    FeatureCrypto]>;
+
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//

diff --git a/test/CodeGen/AArch64/cpus.ll b/test/CodeGen/AArch64/cpus.ll
new file mode 100644 (file)
index 0000000..9d9b5e4
--- /dev/null
+++ b/test/CodeGen/AArch64/cpus.ll
@@ -0,0 +1,13 @@
+; This tests that llc accepts all valid AArch64 CPUs
+
+; RUN: llc < %s -march=aarch64 -mcpu=generic 2>&1 | FileCheck %s
+; RUN: llc < %s -march=aarch64 -mcpu=cortex-a53 2>&1 | FileCheck %s
+; RUN: llc < %s -march=aarch64 -mcpu=cortex-a57 2>&1 | FileCheck %s
+; RUN: llc < %s -march=aarch64 -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID
+
+; CHECK-NOT: {{.*}}  is not a recognized processor for this target
+; INVALID: {{.*}}  is not a recognized processor for this target
+
+define i32 @f(i64 %z) {
+       ret i32 0
+}