PR9838: Fix transform introduced in r127064 to not trigger when only one side of...
authorEli Friedman <eli.friedman@gmail.com>
Thu, 5 May 2011 21:59:18 +0000 (21:59 +0000)
committerEli Friedman <eli.friedman@gmail.com>
Thu, 5 May 2011 21:59:18 +0000 (21:59 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130954 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Analysis/InstructionSimplify.cpp
lib/Transforms/InstCombine/InstCombineCompares.cpp
test/Transforms/InstCombine/icmp.ll

index e7ef6ffd8adeb4a668fbbd16d3e5ea1def2a8b37..22a64e1b3483a483b5455e6baee1ea8064249217 100644 (file)
@@ -1847,7 +1847,7 @@ static Value *SimplifyICmpInst(unsigned Predicate, Value *LHS, Value *RHS,
       // fall-through
     case Instruction::SDiv:
     case Instruction::AShr:
-      if (!LBO->isExact() && !RBO->isExact())
+      if (!LBO->isExact() || !RBO->isExact())
         break;
       if (Value *V = SimplifyICmpInst(Pred, LBO->getOperand(0),
                                       RBO->getOperand(0), TD, DT, MaxRecurse-1))
index bb9b88bfe6a75f6391e0eaf201aca57811e89e9e..b6963c54999c6ed514f647a254ef55b9eb3e05e4 100644 (file)
@@ -2400,7 +2400,7 @@ Instruction *InstCombiner::visitICmpInst(ICmpInst &I) {
         // fall-through
       case Instruction::SDiv:
       case Instruction::AShr:
-        if (!BO0->isExact() && !BO1->isExact())
+        if (!BO0->isExact() || !BO1->isExact())
           break;
         return new ICmpInst(I.getPredicate(), BO0->getOperand(0),
                             BO1->getOperand(0));
index 099540ac745324a5a85dbf6dea1e6f006b4b58e2..1237adee74d67ce3530df2b216cdf01d802c712c 100644 (file)
@@ -510,3 +510,14 @@ define i1 @test52(i32 %x1) nounwind {
   ret i1 %A
 }
 
+; PR9838
+; CHECK: @test53
+; CHECK-NEXT: ashr exact
+; CHECK-NEXT: ashr
+; CHECK-NEXT: icmp
+define i1 @test53(i32 %a, i32 %b) nounwind {
+ %x = ashr exact i32 %a, 30
+ %y = ashr i32 %b, 30
+ %z = icmp eq i32 %x, %y
+ ret i1 %z
+}