fix typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21693 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index aa4ed3b13c3c826b0f68b3f626cd1b3f18826e54..3fcba64e0de21ea73f5ece31a0d9521ae776ed6e 100644 (file)
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -82,7 +82,7 @@ namespace {
       if (!EnableAlphaCT) {
         setOperationAction(ISD::CTPOP    , MVT::i64  , Expand);
         setOperationAction(ISD::CTTZ     , MVT::i64  , Expand);
-        setOperationAction(ISD::CTTZ     , MVT::i64  , Expand);
+        setOperationAction(ISD::CTLZ     , MVT::i64  , Expand);
       }
 
       //If this didn't legalize into a div....

diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index badc89f8148fc380a258b21c60b417ed8167a376..7722ac21df757f680be02de2670a5f1e4e5b70f8 100644 (file)
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -89,6 +89,11 @@ namespace {
       setOperationAction(ISD::FCOS , MVT::f32, Expand);
       setOperationAction(ISD::FSQRT, MVT::f32, Expand);
 
+      //IA64 has these, but they are not implemented
+      setOperationAction(ISD::CTPOP, MVT::i32  , Expand);
+      setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
+      setOperationAction(ISD::CTLZ , MVT::i32  , Expand);
+
       computeRegisterProperties();
 
       addLegalFPImmediate(+0.0);

diff --git a/lib/Target/PowerPC/PPC64ISelPattern.cpp b/lib/Target/PowerPC/PPC64ISelPattern.cpp
index 25fbb98acdf31bf37476ab8a6991b1a8ce712410..54f540fcf1e23ddcf7ef75961de62684025f99d6 100644 (file)
--- a/lib/Target/PowerPC/PPC64ISelPattern.cpp
+++ b/lib/Target/PowerPC/PPC64ISelPattern.cpp
@@ -71,7 +71,7 @@ namespace {
       // PowerPC has these, but they are not implemented
       setOperationAction(ISD::CTPOP, MVT::i64, Expand);
       setOperationAction(ISD::CTTZ , MVT::i64, Expand);
-      setOperationAction(ISD::CTTZ , MVT::i64, Expand);
+      setOperationAction(ISD::CTLZ , MVT::i64, Expand);
 
       setShiftAmountFlavor(Extend);   // shl X, 32 == 0
       addLegalFPImmediate(+0.0); // Necessary for FSEL

diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 6ed33381f358fa69ce744459425e808a9b707e7c..7faaee8464be79a7f5e97bebc90066d4cf9dd21b 100644 (file)
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -72,7 +72,7 @@ namespace {
       //PowerPC has these, but they are not implemented
       setOperationAction(ISD::CTPOP, MVT::i32  , Expand);
       setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
-      setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
+      setOperationAction(ISD::CTLZ , MVT::i32  , Expand);
 
       setSetCCResultContents(ZeroOrOneSetCCResult);
       addLegalFPImmediate(+0.0); // Necessary for FSEL

diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index 07378427497ee5533bdc1600c352e8db944ad2fa..78561fac671eff7eee24d17ee3583ba9da217931 100644 (file)
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -66,7 +66,7 @@ namespace {
       setOperationAction(ISD::SREM             , MVT::f64  , Expand);
       setOperationAction(ISD::CTPOP            , MVT::i32  , Expand);
       setOperationAction(ISD::CTTZ             , MVT::i32  , Expand);
-      setOperationAction(ISD::CTTZ             , MVT::i32  , Expand);
+      setOperationAction(ISD::CTLZ             , MVT::i32  , Expand);
 
       if (!UnsafeFPMath) {
         setOperationAction(ISD::FSIN           , MVT::f64  , Expand);