sub-register indices and outputs a single super register which is formed from
a consecutive sequence of registers.
This is used as register allocation / coalescing aid and it is useful to
represent instructions that output register pairs / quads. For example,
v1024, v1025 = vload <address>
where v1024 and v1025 forms a register pair.
This really should be modelled as
v1024<3>, v1025<4> = vload <address>
but it would violate SSA property before register allocation is done.
Currently we use insert_subreg to form the super register:
v1026 = implicit_def
v1027 - insert_subreg v1026, v1024, 3
v1028 = insert_subreg v1027, v1025, 4
...
= use v1024
= use v1028
But this adds pseudo live interval overlap between v1024 and v1025.
We can now modeled it as
v1024, v1025 = vload <address>
v1026 = REG_SEQUENCE v1024, 3, v1025, 4
...
= use v1024
= use v1026
After coalescing, it will be
v1026<3>, v1025<4> = vload <address>
...
= use v1026<3>
= use v1026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102815
91177308-0d34-0410-b5e6-
96231b3b80d8
let Namespace = "TargetOpcode";
let isAsCheapAsAMove = 1;
}
+
+def REG_SEQUENCE : Instruction {
+ let OutOperandList = (outs unknown:$dst);
+ let InOperandList = (ins variable_ops);
+ let AsmString = "";
+ let Namespace = "TargetOpcode";
+ let neverHasSideEffects = 1;
+ let isAsCheapAsAMove = 1;
+}
}
//===----------------------------------------------------------------------===//
/// instructions are insufficient. The actual MachineInstrs to perform
/// the copy are emitted with the TargetInstrInfo::copyRegToReg hook.
COPY_TO_REGCLASS = 10,
-
+
/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
- DBG_VALUE = 11
+ DBG_VALUE = 11,
+
+ /// REG_SEQUENCE - This variadic instruction is used to form a register that
+ /// represent a consecutive sequence of sub-registers. It's used as register
+ /// coalescing / allocation aid and must be eliminated before code emission.
+ /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
+ /// After register coalescing references of v1024 should be replace with
+ /// v1027:3, v1025 with v1027:4, etc.
+ REG_SEQUENCE = 12
};
} // end namespace TargetOpcode
} // end namespace llvm
R->getName() == "IMPLICIT_DEF" ||
R->getName() == "SUBREG_TO_REG" ||
R->getName() == "COPY_TO_REGCLASS" ||
- R->getName() == "DBG_VALUE") continue;
+ R->getName() == "DBG_VALUE" ||
+ R->getName() == "REG_SEQUENCE") continue;
BitsInit *BI = R->getValueAsBitsInit("Inst");
R->getName() == "IMPLICIT_DEF" ||
R->getName() == "SUBREG_TO_REG" ||
R->getName() == "COPY_TO_REGCLASS" ||
- R->getName() == "DBG_VALUE") {
+ R->getName() == "DBG_VALUE" ||
+ R->getName() == "REG_SEQUENCE") {
o << " 0U,\n";
continue;
}
InstName == "IMPLICIT_DEF" ||
InstName == "SUBREG_TO_REG" ||
InstName == "COPY_TO_REGCLASS" ||
- InstName == "DBG_VALUE") continue;
+ InstName == "DBG_VALUE" ||
+ InstName == "REG_SEQUENCE") continue;
BitsInit *BI = R->getValueAsBitsInit("Inst");
const std::vector<RecordVal> &Vals = R->getValues();
const CodeGenInstruction *COPY_TO_REGCLASS =
GetInstByName("COPY_TO_REGCLASS", Insts);
const CodeGenInstruction *DBG_VALUE = GetInstByName("DBG_VALUE", Insts);
+ const CodeGenInstruction *REG_SEQUENCE = GetInstByName("REG_SEQUENCE", Insts);
// Print out the rest of the instructions now.
InstrsByEnum.push_back(PHI);
InstrsByEnum.push_back(SUBREG_TO_REG);
InstrsByEnum.push_back(COPY_TO_REGCLASS);
InstrsByEnum.push_back(DBG_VALUE);
+ InstrsByEnum.push_back(REG_SEQUENCE);
unsigned EndOfPredefines = InstrsByEnum.size();
CGI != IMPLICIT_DEF &&
CGI != SUBREG_TO_REG &&
CGI != COPY_TO_REGCLASS &&
- CGI != DBG_VALUE)
+ CGI != DBG_VALUE &&
+ CGI != REG_SEQUENCE)
InstrsByEnum.push_back(CGI);
}