Fix PR3826 - InstComb assert with vector shift, by not calling ComputeNumSignBits...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67211 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Transforms/Scalar/InstructionCombining.cpp b/lib/Transforms/Scalar/InstructionCombining.cpp
index fa24d892176230d2038c6d9e936d425b42cf3123..4a7f4c74f3358d60e54cb1aa3000bc3290b6eb10 100644 (file)
--- a/lib/Transforms/Scalar/InstructionCombining.cpp
+++ b/lib/Transforms/Scalar/InstructionCombining.cpp
@@ -7029,15 +7029,16 @@ Instruction *InstCombiner::visitAShr(BinaryOperator &I) {
       return ReplaceInstUsesWith(I, CSI);
   
   // See if we can turn a signed shr into an unsigned shr.
-  if (!isa<VectorType>(I.getType()) &&
-      MaskedValueIsZero(Op0,
+  if (!isa<VectorType>(I.getType())) {
+    if (MaskedValueIsZero(Op0,
                       APInt::getSignBit(I.getType()->getPrimitiveSizeInBits())))
-    return BinaryOperator::CreateLShr(Op0, I.getOperand(1));
+      return BinaryOperator::CreateLShr(Op0, I.getOperand(1));
 
-  // Arithmetic shifting an all-sign-bit value is a no-op.
-  unsigned NumSignBits = ComputeNumSignBits(Op0);
-  if (NumSignBits == Op0->getType()->getPrimitiveSizeInBits())
-    return ReplaceInstUsesWith(I, Op0);
+    // Arithmetic shifting an all-sign-bit value is a no-op.
+    unsigned NumSignBits = ComputeNumSignBits(Op0);
+    if (NumSignBits == Op0->getType()->getPrimitiveSizeInBits())
+      return ReplaceInstUsesWith(I, Op0);
+  }
 
   return 0;
 }

diff --git a/test/Transforms/InstCombine/2009-03-18-vector-ashr-crash.ll b/test/Transforms/InstCombine/2009-03-18-vector-ashr-crash.ll
new file mode 100644 (file)
index 0000000..ae690cf
--- /dev/null
+++ b/test/Transforms/InstCombine/2009-03-18-vector-ashr-crash.ll
@@ -0,0 +1,11 @@
+; RUN: llvm-as < %s | opt -instcombine | llvm-dis
+; PR3826
+
+define void @0(<4 x i16>*, <4 x i16>*) {
+       %3 = alloca <4 x i16>*          ; <<4 x i16>**> [#uses=1]
+       %4 = load <4 x i16>* null, align 1              ; <<4 x i16>> [#uses=1]
+       %5 = ashr <4 x i16> %4, <i16 5, i16 5, i16 5, i16 5>            ; <<4 x i16>> [#uses=1]
+       %6 = load <4 x i16>** %3                ; <<4 x i16>*> [#uses=1]
+       store <4 x i16> %5, <4 x i16>* %6, align 1
+       ret void
+}