Emit 32-bit register names instead of 64-bit register names if the target does
not have 64-bit general purpose registers.
<rdar://problem/
14653996>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205067
91177308-0d34-0410-b5e6-
96231b3b80d8
case 'k': // Print SImode register
Reg = getX86SubSuperRegister(Reg, MVT::i32);
break;
- case 'q': // Print DImode register
- // FIXME: gcc will actually print e instead of r for 32-bit.
- Reg = getX86SubSuperRegister(Reg, MVT::i64);
+ case 'q':
+ // Print 64-bit register names if 64-bit integer registers are available.
+ // Otherwise, print 32-bit register names.
+ MVT::SimpleValueType Ty = P.getSubtarget().is64Bit() ? MVT::i64 : MVT::i32;
+ Reg = getX86SubSuperRegister(Reg, Ty);
break;
}
--- /dev/null
+; RUN: llc < %s -march=x86 -no-integrated-as | FileCheck %s
+
+; If the target does not have 64-bit integer registers, emit 32-bit register
+; names.
+
+; CHECK: movq (%e{{[abcd]}}x, %ebx, 4)
+
+define void @q_modifier(i32* %p) {
+entry:
+ tail call void asm sideeffect "movq (${0:q}, %ebx, 4), %mm0", "r,~{dirflag},~{fpsr},~{flags}"(i32* %p)
+ ret void
+}