Specify that the high bit of the alignment field is fixed to 0 on these instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143220 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index 75418aa97580b09192cc80addc4d79a09ba182f7..3023a3419ddfc5e40f337fed062082837d586cc4 100644 (file)
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -389,7 +389,7 @@ multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
                      "vld1", Dt, "$Vd, $Rn!",
                      "$Rn.addr = $wb", []> {
     let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
-    let Inst{5-4} = Rn{5-4};
+    let Inst{4} = Rn{4};
     let DecoderMethod = "DecodeVLDInstruction";
     let AsmMatchConverter = "cvtVLDwbFixed";
   }
@@ -397,7 +397,7 @@ multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
                         (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
                         "vld1", Dt, "$Vd, $Rn, $Rm",
                         "$Rn.addr = $wb", []> {
-    let Inst{5-4} = Rn{5-4};
+    let Inst{4} = Rn{4};
     let DecoderMethod = "DecodeVLDInstruction";
     let AsmMatchConverter = "cvtVLDwbRegister";
   }