InstCombine: Remove overzealous asserts
authorDavid Majnemer <david.majnemer@gmail.com>
Sat, 25 Oct 2014 07:13:13 +0000 (07:13 +0000)
committerDavid Majnemer <david.majnemer@gmail.com>
Sat, 25 Oct 2014 07:13:13 +0000 (07:13 +0000)
These asserts can trigger if the worklist iteration order is
sufficiently unlucky.  Instead of adding special case logic to handle
these edge conditions, just bail out on trying to transform them:
InstSimplify will get them when it reaches them on the worklist.

This fixes PR21378.

N.B.  No test case is included because any test would rely on the
fragile worklist iteration order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220612 91177308-0d34-0410-b5e6-96231b3b80d8


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