ARM RSCS* don't need explicit TableGen decoder checks.

They've been pseudos for a while now, so the decoder will never see
them in the first place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134101 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/utils/TableGen/ARMDecoderEmitter.cpp b/utils/TableGen/ARMDecoderEmitter.cpp
index cccfefde703215454e3b23ad854cd7f631a5874f..a320e77b2875fc1792c02d2febed1df997a4e0ea 100644 (file)
--- a/utils/TableGen/ARMDecoderEmitter.cpp
+++ b/utils/TableGen/ARMDecoderEmitter.cpp
@@ -1592,10 +1592,6 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
     // The following special cases are for conflict resolutions.
     //
 
-    // RSCSri and RSCSrs set the 's' bit, but are not predicated.  We are
-    // better off using the generic RSCri and RSCrs instructions.
-    if (Name == "RSCSri" || Name == "RSCSrs") return false;
-
     // A8-598: VEXT
     // Vector Extract extracts elements from the bottom end of the second
     // operand vector and the top end of the first, concatenates them and