OpInfo[1].RegClass == ARM::GPRRegClassID &&
"Expect >= 3 operands and first two as reg operands");
OpInfo[1].RegClass == ARM::GPRRegClassID &&
"Expect >= 3 operands and first two as reg operands");
- bool ThreeReg = (OpInfo[2].RegClass == ARM::GPRRegClassID);
+ bool ThreeReg = (OpInfo[2].RegClass > 0);
bool TIED_TO = ThreeReg && TID.getOperandConstraint(2, TOI::TIED_TO) != -1;
bool Imm12 = !ThreeReg && slice(insn, 23, 23) == 1; // ARMInstrThumb2.td
bool TIED_TO = ThreeReg && TID.getOperandConstraint(2, TOI::TIED_TO) != -1;
bool Imm12 = !ThreeReg && slice(insn, 23, 23) == 1; // ARMInstrThumb2.td
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ // This could be an offset register or a TIED_TO register.
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B,OpInfo[OpIdx].RegClass,
# CHECK: tbb [r5, r4]
0xd5 0xe8 0x04 0xf0
# CHECK: tbb [r5, r4]
0xd5 0xe8 0x04 0xf0
+
+# CHECK: ldr.w r4, [sp, r4, lsl #3]
+0x5d 0xf8 0x34 0x40
+
+# CHECK: ldr.w r5, [r6, #30]
+0x56 0xf8 0x1e 0x56