[ARM] Use patterns instead of hardcoded regs in test. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228259 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/ARM/big-endian-neon-extend.ll b/test/CodeGen/ARM/big-endian-neon-extend.ll
index fd3016da509056fb06a3b7c5d8cdeb47c236e618..1498356eb971d365b4e95a9f173d8edfdf2f5ca6 100644 (file)
--- a/test/CodeGen/ARM/big-endian-neon-extend.ll
+++ b/test/CodeGen/ARM/big-endian-neon-extend.ll
@@ -12,7 +12,7 @@ define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr
 ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
 ; CHECK-NEXT: vand      [[QREG]], [[QREG]], [[MASK]]
 ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
-; CHECK-NEXT: vst1.64   {[[REG]], d17}, [r1]
+; CHECK-NEXT: vst1.64   {[[REG]], {{d[0-9]+}}}, [r1]
 ; CHECK-NEXT: bx        lr
   %1 = load <2 x i8>* %loadaddr
   %2 = zext <2 x i8> %1 to <2 x i64>
@@ -31,7 +31,7 @@ define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeadd
 ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
 ; CHECK-NEXT: vand      [[QREG]], [[QREG]], [[MASK]]
 ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
-; CHECK-NEXT: vst1.64   {[[REG]], d17}, [r1]
+; CHECK-NEXT: vst1.64   {[[REG]], {{d[0-9]+}}}, [r1]
 ; CHECK-NEXT: bx        lr
   %1 = load <2 x i16>* %loadaddr
   %2 = zext <2 x i16> %1 to <2 x i64>
@@ -76,8 +76,8 @@ define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr
 ; CHECK-NEXT: vmovl.u8  [[QREG:q[0-9]+]], [[REG]]
 ; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
 ; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
-; CHECK-NEXT: vuzp.16   [[REG]], d17
-; CHECK-NEXT: vrev32.16 [[REG]], d17
+; CHECK-NEXT: vuzp.16   [[REG]], {{d[0-9]+}}
+; CHECK-NEXT: vrev32.16 [[REG]], {{d[0-9]+}}
 ; CHECK-NEXT: vst1.32   {[[REG]][0]}, [r1:32]
 ; CHECK-NEXT: bx        lr
   %1 = load <2 x i8>* %loadaddr
@@ -93,7 +93,7 @@ define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr
 ; CHECK-NEXT: vmovl.u8  [[QREG:q[0-9]+]], [[REG]]
 ; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
 ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
-; CHECK-NEXT: vst1.64   {[[REG]], d17}, [r1]
+; CHECK-NEXT: vst1.64   {[[REG]], {{d[0-9]+}}}, [r1]
 ; CHECK-NEXT: bx        lr
   %1 = load <4 x i8>* %loadaddr
   %2 = zext <4 x i8> %1 to <4 x i32>