"$addr.base = $wb", []>;
// T2Ipl (Preload Data/Instruction) signals the memory system of possible future
-// data/instruction access. These are for disassembly only.
+// data/instruction access.
// instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
// (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
let DecoderMethod = "DecodeT2LoadShift";
}
+ // FIXME: We should have a separate 'pci' variant here. As-is we represent
+ // it via the i12 variant, which it's related to, but that means we can
+ // represent negative immediates, which aren't legal for anything except
+ // the 'pci' case (Rn == 15).
}
defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
def : t2InstAlias<"ldrsh${p} $Rt, $addr",
(t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
+def : t2InstAlias<"ldr${p} $Rt, $addr",
+ (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
+def : t2InstAlias<"ldrb${p} $Rt, $addr",
+ (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
+def : t2InstAlias<"ldrh${p} $Rt, $addr",
+ (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
+def : t2InstAlias<"ldrsb${p} $Rt, $addr",
+ (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
+def : t2InstAlias<"ldrsh${p} $Rt, $addr",
+ (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
+
// Alias for MVN without the ".w" optional width specifier.
def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
(t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
@ LDR(literal)
@------------------------------------------------------------------------------
ldr.w r5, _foo
+ ldr lr, (_strcmp-4)
@ CHECK: ldr.w r5, _foo @ encoding: [0x5f'A',0xf8'A',A,0x50'A']
- @ fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12
+@ CHECK: @ fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12
+@ CHECK: ldr.w lr, _strcmp-4 @ encoding: [0x5f'A',0xf8'A',A,0xe0'A']
+@ CHECK: @ fixup A - offset: 0, value: _strcmp-4, kind: fixup_t2_ldst_pcrel_12
@------------------------------------------------------------------------------
@------------------------------------------------------------------------------
ldrh r5, _bar
-@ CHECK: ldrh.w r5, _bar @ encoding: [0xbf'A',0xf8'A',A,0x50'A']
+@ CHECK: ldrh.w r5, _bar @ encoding: [0x3f'A',0xf8'A',A,0x50'A']
@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12
@------------------------------------------------------------------------------
ldrsb r5, _bar
-@ CHECK: ldrsb.w r5, _bar @ encoding: [0x9f'A',0xf9'A',A,0x50'A']
+@ CHECK: ldrsb.w r5, _bar @ encoding: [0x1f'A',0xf9'A',A,0x50'A']
@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12
@------------------------------------------------------------------------------
ldrsh r5, _bar
-@ CHECK: ldrsh.w r5, _bar @ encoding: [0xbf'A',0xf9'A',A,0x50'A']
+@ CHECK: ldrsh.w r5, _bar @ encoding: [0x3f'A',0xf9'A',A,0x50'A']
@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12
@ TEMPORARILY DISABLED:
@------------------------------------------------------------------------------
@ PLD(literal)
@------------------------------------------------------------------------------
- pld _foo
+@ pld _foo
-@ CHECK: pld _foo @ encoding: [0x9f'A',0xf8'A',A,0xf0'A']
+@ FIXME: pld _foo @ encoding: [0x9f'A',0xf8'A',A,0xf0'A']
@ fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12
@------------------------------------------------------------------------------
@ PLI(literal)
@------------------------------------------------------------------------------
- pli _foo
+@ pli _foo
-@ CHECK: pli _foo @ encoding: [0x9f'A',0xf9'A',A,0xf0'A']
+@ FIXME: pli _foo @ encoding: [0x9f'A',0xf9'A',A,0xf0'A']
@ fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12