defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,
Requires<[HasV9, HasHardQuad]>;
+let DecoderMethod = "DecodeStoreFP" in
+ let Defs = [FSR] in {
+ let rd = 0 in {
+ def STFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins),
+ "st %fsr, [$addr]", []>;
+ def STFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins),
+ "st %fsr, [$addr]", []>;
+ }
+ let rd = 1 in {
+ def STXFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins),
+ "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
+ def STXFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins),
+ "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
+ }
+ }
+
// Section B.8 - SWAP Register with Memory Instruction
// (Atomic swap)
let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
! CHECK: ld [%g2+%i5], %fsr ! encoding: [0xc1,0x08,0x80,0x1d]
ld [%g2 + %i5],%fsr
+
+ ! CHECK: st %fsr, [%g2+20] ! encoding: [0xc1,0x28,0xa0,0x14]
+ st %fsr,[%g2 + 20]
+
+ ! CHECK: st %fsr, [%g2+%i5] ! encoding: [0xc1,0x28,0x80,0x1d]
+ st %fsr,[%g2 + %i5]
! V8-NEXT: ldx [%g2 + %i5],%fsr
! V9: ldx [%g2+%i5], %fsr ! encoding: [0xc3,0x08,0x80,0x1d]
ldx [%g2 + %i5],%fsr
+
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: stx %fsr,[%g2 + 20]
+ ! V9: stx %fsr, [%g2+20] ! encoding: [0xc3,0x28,0xa0,0x14]
+ stx %fsr,[%g2 + 20]
+
+ ! V8: error: instruction requires a CPU feature not currently enabled
+ ! V8-NEXT: stx %fsr,[%g2 + %i5]
+ ! V9: stx %fsr, [%g2+%i5] ! encoding: [0xc3,0x28,0x80,0x1d]
+ stx %fsr,[%g2 + %i5]