Prefer LMUL to MACCU as LMUL has no tied operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98153 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/lib/Target/XCore/XCoreISelDAGToDAG.cpp
index 12967d42de46a8fe568364937d716f6d3b9968d8..29a6ab77d01303e7b52b6683214d9e23e697873d 100644 (file)
--- a/lib/Target/XCore/XCoreISelDAGToDAG.cpp
+++ b/lib/Target/XCore/XCoreISelDAGToDAG.cpp
@@ -220,6 +220,12 @@ SDNode *XCoreDAGToDAGISel::Select(SDNode *N) {
         return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32,
                                       Ops, 4);
       }
+      case XCoreISD::LMUL: {
+        SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
+                          N->getOperand(2), N->getOperand(3) };
+        return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32,
+                                      Ops, 4);
+      }
       // Other cases are autogenerated.
     }
   }

diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp
index 70ceadd4df5873a8d6e30790e06bab4dc955ad34..d27adf40f6c0061c7a3a716ae1d13c20f1cd2c9f 100644 (file)
--- a/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/lib/Target/XCore/XCoreISelLowering.cpp
@@ -54,6 +54,7 @@ getTargetNodeName(unsigned Opcode) const
     case XCoreISD::RETSP             : return "XCoreISD::RETSP";
     case XCoreISD::LADD              : return "XCoreISD::LADD";
     case XCoreISD::LSUB              : return "XCoreISD::LSUB";
+    case XCoreISD::LMUL              : return "XCoreISD::LMUL";
     case XCoreISD::MACCU             : return "XCoreISD::MACCU";
     case XCoreISD::MACCS             : return "XCoreISD::MACCS";
     case XCoreISD::BR_JT             : return "XCoreISD::BR_JT";
@@ -573,9 +574,9 @@ LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG)
   SDValue LHS = Op.getOperand(0);
   SDValue RHS = Op.getOperand(1);
   SDValue Zero = DAG.getConstant(0, MVT::i32);
-  SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
-                           DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,
-                           LHS, RHS);
+  SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
+                           DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,
+                           Zero, Zero);
   SDValue Lo(Hi.getNode(), 1);
   SDValue Ops[] = { Lo, Hi };
   return DAG.getMergeValues(Ops, 2, dl);

diff --git a/lib/Target/XCore/XCoreISelLowering.h b/lib/Target/XCore/XCoreISelLowering.h
index 6b467c3f9c33799404e7fdb7181788ca6481d8f2..69281383867f317fb3b28be12f55e10926cac452 100644 (file)
--- a/lib/Target/XCore/XCoreISelLowering.h
+++ b/lib/Target/XCore/XCoreISelLowering.h
@@ -54,6 +54,9 @@ namespace llvm {
       // Corresponds to LSUB instruction
       LSUB,
 
+      // Corresponds to LMUL instruction
+      LMUL,
+
       // Corresponds to MACCU instruction
       MACCU,
 

diff --git a/test/CodeGen/XCore/mul64.ll b/test/CodeGen/XCore/mul64.ll
index c42c2f59cd34feb123af8ff0977a36036a0bffe1..c06fe5a20b3aec889c35aaea0836388060cf3cd1 100644 (file)
--- a/test/CodeGen/XCore/mul64.ll
+++ b/test/CodeGen/XCore/mul64.ll
@@ -8,10 +8,7 @@ entry:
 }
 ; CHECK: umul_lohi:
 ; CHECK: ldc r2, 0
-; CHECK-NEXT: mov r3, r2
-; CHECK-NEXT: maccu r2, r3, r1, r0
-; CHECK-NEXT: mov r0, r3
-; CHECK-NEXT: mov r1, r2
+; CHECK-NEXT: lmul r1, r0, r1, r0, r2, r2
 ; CHECK-NEXT: retsp 0
 
 define i64 @smul_lohi(i32 %a, i32 %b) {