Avoid resetting the UseSoftFloat and FloatABIType on the TargetMachine

Options struct and move the comment to inMips16HardFloat. Use the
fact that we now know whether or not we cared about soft float to
set the libcalls.
Accordingly rename mipsSEUsesSoftFloat to abiUsesSoftFloat and
propagate since it's no longer CPU specific.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213335 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 2bedb5960ffb8537a53a3bed76959847ad78592e..53b30f9210b06b1320d76ea0566737ec9066ed57 100644 (file)
--- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -292,7 +292,7 @@ public:
     return STI.getFeatureBits() & Mips::FeatureMips16;
   }
   // TODO: see how can we get this info.
     return STI.getFeatureBits() & Mips::FeatureMips16;
   }
   // TODO: see how can we get this info.

-  bool mipsSEUsesSoftFloat() const { return false; }
+  bool abiUsesSoftFloat() const { return false; }

 
   /// Warn if RegNo is the current assembler temporary.
   void WarnIfAssemblerTemporary(int RegNo, SMLoc Loc);
 
   /// Warn if RegNo is the current assembler temporary.
   void WarnIfAssemblerTemporary(int RegNo, SMLoc Loc);

diff --git a/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h b/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h
index e56efd04ac1434dbd919b8e537da962827eab2cf..ea5bc12b07406b875aee320d2a860047b093307a 100644 (file)
--- a/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h
+++ b/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h
@@ -181,7 +181,7 @@ public:
 
   template <class PredicateLibrary>
   void setCPR1SizeFromPredicates(const PredicateLibrary &P) {
 
   template <class PredicateLibrary>
   void setCPR1SizeFromPredicates(const PredicateLibrary &P) {

-    if (P.mipsSEUsesSoftFloat())
+    if (P.abiUsesSoftFloat())

       CPR1Size = AFL_REG_NONE;
     else if (P.hasMSA())
       CPR1Size = AFL_REG_128;
       CPR1Size = AFL_REG_NONE;
     else if (P.hasMSA())
       CPR1Size = AFL_REG_128;

diff --git a/lib/Target/Mips/Mips16ISelLowering.cpp b/lib/Target/Mips/Mips16ISelLowering.cpp
index 81a05df1a70d652e274607fa223b98693dd9bf9e..118612ae569017dc7f5a46f40d3c14c07e0b3d5f 100644 (file)
--- a/lib/Target/Mips/Mips16ISelLowering.cpp
+++ b/lib/Target/Mips/Mips16ISelLowering.cpp
@@ -124,7 +124,7 @@ Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM)
   // Set up the register classes
   addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
 
   // Set up the register classes
   addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
 

-  if (Subtarget->inMips16HardFloat())
+  if (!TM.Options.UseSoftFloat)

     setMips16HardFloatLibCalls();
 
   setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Expand);
     setMips16HardFloatLibCalls();
 
   setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Expand);

diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index b7af2d4aaf48240f8fe673a043c99cb841d25406..179e30a81518c047e8e2caa11197a514685245a0 100644 (file)
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -2414,7 +2414,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
                     CCInfo, SpecialCallingConv);
 
   MipsCCInfo.analyzeCallOperands(Outs, IsVarArg,
                     CCInfo, SpecialCallingConv);
 
   MipsCCInfo.analyzeCallOperands(Outs, IsVarArg,

-                                 Subtarget->mipsSEUsesSoftFloat(),
+                                 Subtarget->abiUsesSoftFloat(),

                                  Callee.getNode(), CLI.getArgs());
 
   // Get a count of how many bytes are to be pushed on the stack.
                                  Callee.getNode(), CLI.getArgs());
 
   // Get a count of how many bytes are to be pushed on the stack.


@@ -2615,7 +2615,7 @@ MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
   MipsCC MipsCCInfo(CallConv, Subtarget->isABI_O32(), Subtarget->isFP64bit(),
                     CCInfo);
 
   MipsCC MipsCCInfo(CallConv, Subtarget->isABI_O32(), Subtarget->isFP64bit(),
                     CCInfo);
 

-  MipsCCInfo.analyzeCallResult(Ins, Subtarget->mipsSEUsesSoftFloat(),
+  MipsCCInfo.analyzeCallResult(Ins, Subtarget->abiUsesSoftFloat(),

                                CallNode, RetTy);
 
   // Copy all of the result registers out of their specified physreg.
                                CallNode, RetTy);
 
   // Copy all of the result registers out of their specified physreg.


@@ -2664,7 +2664,7 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
                     CCInfo);
   Function::const_arg_iterator FuncArg =
     DAG.getMachineFunction().getFunction()->arg_begin();
                     CCInfo);
   Function::const_arg_iterator FuncArg =
     DAG.getMachineFunction().getFunction()->arg_begin();

-  bool UseSoftFloat = Subtarget->mipsSEUsesSoftFloat();
+  bool UseSoftFloat = Subtarget->abiUsesSoftFloat();

 
   MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg);
   MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
 
   MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg);
   MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),


@@ -2817,7 +2817,7 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
                     CCInfo);
 
   // Analyze return values.
                     CCInfo);
 
   // Analyze return values.

-  MipsCCInfo.analyzeReturn(Outs, Subtarget->mipsSEUsesSoftFloat(),
+  MipsCCInfo.analyzeReturn(Outs, Subtarget->abiUsesSoftFloat(),

                            MF.getFunction()->getReturnType());
 
   SDValue Flag;
                            MF.getFunction()->getReturnType());
 
   SDValue Flag;

diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp
index be4ca862540e4046f5e3b548d95e82ff8fe7a6c8..45628afef28ecb710ebc6bd5958461bf6c75fb1b 100644 (file)
--- a/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -101,7 +101,7 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
     setTargetDAGCombine(ISD::XOR);
   }
 
     setTargetDAGCombine(ISD::XOR);
   }
 

-  if (!Subtarget->mipsSEUsesSoftFloat()) {
+  if (!Subtarget->abiUsesSoftFloat()) {

     addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
 
     // When dealing with single precision only, use libcalls
     addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
 
     // When dealing with single precision only, use libcalls

diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp
index d63b712f83dafc5a6c998085b6222db999ba069c..2cb97ae7f72f0e475d25116be33bd624dcc83995 100644 (file)
--- a/lib/Target/Mips/MipsSubtarget.cpp
+++ b/lib/Target/Mips/MipsSubtarget.cpp
@@ -200,15 +200,8 @@ MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
   // Initialize scheduling itinerary for the specified CPU.
   InstrItins = getInstrItineraryForCPU(CPUName);
 
   // Initialize scheduling itinerary for the specified CPU.
   InstrItins = getInstrItineraryForCPU(CPUName);
 

-  if (InMips16Mode && !TM->Options.UseSoftFloat) {
-    // Hard float for mips16 means essentially to compile as soft float
-    // but to use a runtime library for soft float that is written with
-    // native mips32 floating point instructions (those runtime routines
-    // run in mips32 hard float mode).
-    TM->Options.UseSoftFloat = true;
-    TM->Options.FloatABIType = FloatABI::Soft;
+  if (InMips16Mode && !TM->Options.UseSoftFloat)

     InMips16HardFloat = true;
     InMips16HardFloat = true;

-  }

 
   return *this;
 }
 
   return *this;
 }


@@ -293,7 +286,7 @@ void MipsSubtarget::setHelperClassesMipsSE() {
   assert(FrameLowering && "null frame lowering SE");
 }
 
   assert(FrameLowering && "null frame lowering SE");
 }
 

-bool MipsSubtarget::mipsSEUsesSoftFloat() const {
+bool MipsSubtarget::abiUsesSoftFloat() const {

   return TM->Options.UseSoftFloat && !InMips16HardFloat;
 }
 
   return TM->Options.UseSoftFloat && !InMips16HardFloat;
 }
 

diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h
index 944e629898b62919057e3c52a33bdc6bed1e0d93..7810e0ee7fa2fa0a0b225df5fb8774927ac3f4fe 100644 (file)
--- a/lib/Target/Mips/MipsSubtarget.h
+++ b/lib/Target/Mips/MipsSubtarget.h
@@ -234,6 +234,10 @@ public:
   bool inMips16ModeDefault() const {
     return InMips16Mode;
   }
   bool inMips16ModeDefault() const {
     return InMips16Mode;
   }

+  // Hard float for mips16 means essentially to compile as soft float
+  // but to use a runtime library for soft float that is written with
+  // native mips32 floating point instructions (those runtime routines
+  // run in mips32 hard float mode).

   bool inMips16HardFloat() const {
     return inMips16Mode() && InMips16HardFloat;
   }
   bool inMips16HardFloat() const {
     return inMips16Mode() && InMips16HardFloat;
   }


@@ -246,7 +250,7 @@ public:
 
   bool hasStandardEncoding() const { return !inMips16Mode(); }
 
 
   bool hasStandardEncoding() const { return !inMips16Mode(); }
 

-  bool mipsSEUsesSoftFloat() const;
+  bool abiUsesSoftFloat() const;

 
   bool enableLongBranchPass() const {
     return hasStandardEncoding() || allowMixed16_32();
 
   bool enableLongBranchPass() const {
     return hasStandardEncoding() || allowMixed16_32();