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Use PairDRegs to implement ConcatVectors. No functionality change.
author
Bob Wilson
<bob.wilson@apple.com>
Fri, 17 Dec 2010 01:21:08 +0000
(
01:21
+0000)
committer
Bob Wilson
<bob.wilson@apple.com>
Fri, 17 Dec 2010 01:21:08 +0000
(
01:21
+0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122017
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/ARM/ARMISelDAGToDAG.cpp
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diff --git
a/lib/Target/ARM/ARMISelDAGToDAG.cpp
b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 991814ed114fa7df16388710fa86ed02414e23e1..e5a8d9193165f06124508b3706edb64a1f57f1d0 100644
(file)
--- a/
lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/
lib/Target/ARM/ARMISelDAGToDAG.cpp
@@
-2141,13
+2141,7
@@
SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
EVT VT = N->getValueType(0);
if (!VT.is128BitVector() || N->getNumOperands() != 2)
llvm_unreachable("unexpected CONCAT_VECTORS");
EVT VT = N->getValueType(0);
if (!VT.is128BitVector() || N->getNumOperands() != 2)
llvm_unreachable("unexpected CONCAT_VECTORS");
- DebugLoc dl = N->getDebugLoc();
- SDValue V0 = N->getOperand(0);
- SDValue V1 = N->getOperand(1);
- SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
- SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
- const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
- return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
+ return PairDRegs(VT, N->getOperand(0), N->getOperand(1));
}
SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
}
SDNode *ARMDAGToDAGISel::Select(SDNode *N) {