Updated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35229 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/README.txt b/lib/Target/ARM/README.txt
index c155e20633432926dc710c0fd85936ac9ffbea98..8af07ccffb6aa7aeb6bb0dad2a224ff21c5df680 100644 (file)
--- a/lib/Target/ARM/README.txt
+++ b/lib/Target/ARM/README.txt
@@ -470,4 +470,9 @@ More register scavenging work:
 
 //===---------------------------------------------------------------------===//
 
-Teach LSR about ARM addressing modes.
+More LSR enhancements possible:
+
+1. Teach LSR about pre- and post- indexed ops to allow iv increment be merged
+   in a load / store.
+2. Allow iv reuse even when a type conversion is required. For example, i8
+   and i32 load / store addressing modes are identical.