Fix an issue where the ordering of blocks within a function could lead to different...

graphs being produced.  The cause was that we were incorrectly marking sigma instructions as
processed after handling the sigma-specific constraints for them, potentially neglecting to
process them as normal instructions as well.

Unfortunately, the testcase that inspired this still doesn't work because of a bug in the solver,
which is next on the list to debug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86486 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Transforms/Scalar/ABCD.cpp b/lib/Transforms/Scalar/ABCD.cpp
index c8541d72a4d376fb785792a4e07142c3c2d01ed2..cc4683a52a8e5edd4f5c61306750afef3d9af146 100644 (file)
--- a/lib/Transforms/Scalar/ABCD.cpp
+++ b/lib/Transforms/Scalar/ABCD.cpp
@@ -796,13 +796,15 @@ void ABCD::createConstraintSigInst(Instruction *I_op, BasicBlock *BB_succ_t,
     int32_t width = cast<IntegerType>((*SIG_op_t)->getType())->getBitWidth();
     inequality_graph.addEdge(I_op, *SIG_op_t, APInt(width, 0), true);
     inequality_graph.addEdge(*SIG_op_t, I_op, APInt(width, 0), false);
-    created.insert(*SIG_op_t);
+    if (created.insert(*SIG_op_t))
+      createConstraintPHINode(cast<PHINode>(*SIG_op_t));
   }
   if (*SIG_op_f) {
     int32_t width = cast<IntegerType>((*SIG_op_f)->getType())->getBitWidth();
     inequality_graph.addEdge(I_op, *SIG_op_f, APInt(width, 0), true);
     inequality_graph.addEdge(*SIG_op_f, I_op, APInt(width, 0), false);
-    created.insert(*SIG_op_f);
+    if (created.insert(*SIG_op_f))
+      createConstraintPHINode(cast<PHINode>(*SIG_op_f));
   }
 }