Generate the fchs instruction to negate a floating point number

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11078 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp
index fd4c44f99e0eb2874c24027eed1e7ddae1e727b8..abfcad15668e42f6783f90f84029abcae4fe234b 100644 (file)
--- a/lib/Target/X86/InstSelectSimple.cpp
+++ b/lib/Target/X86/InstSelectSimple.cpp
@@ -1227,7 +1227,13 @@ void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
           return;
         }
       }
-    }
+    } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
+      if (CFP->isExactlyValue(-0.0)) {
+        // -0.0 - X === -X
+        unsigned op1Reg = getReg(Op1, MBB, IP);
+        BMI(MBB, IP, X86::FCHS, 1, DestReg).addReg(op1Reg);
+        return;
+      }
 
   if (!isa<ConstantInt>(Op1) || Class == cLong) {
     static const unsigned OpcodeTab[][4] = {

diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp
index fd4c44f99e0eb2874c24027eed1e7ddae1e727b8..abfcad15668e42f6783f90f84029abcae4fe234b 100644 (file)
--- a/lib/Target/X86/X86ISelSimple.cpp
+++ b/lib/Target/X86/X86ISelSimple.cpp
@@ -1227,7 +1227,13 @@ void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
           return;
         }
       }
-    }
+    } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
+      if (CFP->isExactlyValue(-0.0)) {
+        // -0.0 - X === -X
+        unsigned op1Reg = getReg(Op1, MBB, IP);
+        BMI(MBB, IP, X86::FCHS, 1, DestReg).addReg(op1Reg);
+        return;
+      }
 
   if (!isa<ConstantInt>(Op1) || Class == cLong) {
     static const unsigned OpcodeTab[][4] = {

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 6cd514bad87230c746fa29d0925305841d2bcd3e..1dc63bb7828e3d04050828c4ec63d76c0342f0e3 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -388,6 +388,10 @@ def MOVZXr32r16: X86Inst<"movzx", 0xB7, MRMSrcReg, Arg8>, TB;         // R32 = z
 class FPInst<string n, bits<8> o, Format F, ArgType t, FPFormat fp>
   : X86Inst<n, o, F, t> { let FPForm = fp; let FPFormBits = FPForm.Value; }
 
+// Pseudo instructions for floating point.  We use these pseudo instructions
+// because they can be expanded by the fp spackifier into one of many different
+// forms of instructions for doing these operations.  Until the stackifier runs,
+// we prefer to be abstract.
 def FpMOV : FPInst<"FMOV", 0, Pseudo, ArgF80, SpecialFP>;   // f1 = fmov f2
 def FpADD : FPInst<"FADD", 0, Pseudo, ArgF80, TwoArgFP>;    // f1 = fadd f2, f3
 def FpSUB : FPInst<"FSUB", 0, Pseudo, ArgF80, TwoArgFP>;    // f1 = fsub f2, f3
@@ -429,6 +433,10 @@ def FXCH     : FPInst<"fxch",    0xC8, AddRegFrm, ArgF80, NotFP>, D9;      // fx
 def FLD0 : FPInst<"fldz", 0xEE, RawFrm, ArgF80, ZeroArgFP>, D9;
 def FLD1 : FPInst<"fld1", 0xE8, RawFrm, ArgF80, ZeroArgFP>, D9;
 
+
+// Unary read-modify-write operations...
+def FCHS : FPInst<"fchs", 0xE0, RawFrm, ArgF80, OneArgFPRW>, D9, Imp<[ST0],[ST0]>;  // f1 = fchs f2
+
 // Binary arithmetic operations...
 class FPST0rInst<string n, bits<8> o>
   : X86Inst<n, o, AddRegFrm, ArgF80>, D8 {